DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: the Application filed July 18, 2024.
Claims 1-20 are pending. Claims 1, 8 and 14 are independent.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement (IDS) filed on August 2, 2024. This IDS has been considered.
Drawings
The drawings are objected to because:
Figures 1A-15D should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g).
Applicant’s Figures 1A-15D are identical to U.S. 11,211,392 Figures 1A-15D.
Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
Claims 1-4 and 7 means limitations (“control means”) has/have been interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because it uses/they use a generic placeholder “means” coupled with functional language “configured to” without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier.
Because this/these claim limitations(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C 112(f), sixth paragraph, applicant may: (1) amend the claim limitations(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 8-10 and 14-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (U.S. 10,957,394; hereinafter “Chen”).
Regarding independent claim 1, Chen discloses a memory apparatus (Fig. 1A), comprising:
memory cells (Fig. 7A) each connected to one of a plurality of word lines (Fig. 7A: WLs) and configured to retain a threshold voltage corresponding to one of a plurality of data states (see col. 19, ll. 12-27), the memory cells disposed in memory holes defining channels (see col. 14, ll. 9-36); and
a control means (Fig. 1A: 110, 122, 124, 128 and 132) configured to:
generate holes by applying a hole pre-charge voltage to the channels of the memory holes in a pre-charge phase of a program operation of the memory cells in the memory holes (see Abstract), and
following the pre-charge phase, apply one of a series of programming pulses of a program voltage to selected ones of the plurality of word lines to program the memory cells connected thereto (Fig. 11: step 1105, see also Fig. 13A).
Regarding claim 2, Chen discloses wherein the plurality of word lines and a plurality of dielectric layers extend horizontally and overlay one another in an alternating fashion in a stack (see col. 2, ll. 44-52), the memory holes extend vertically through the stack (see col. 2, ll. 44-58, see also Fig. 6), the memory cells are connected in series between at least one drain-side select gate transistor on a drain-side of each of the memory holes (Fig. 7A: 716) and a source-side select gate transistor on a source-side of each of the memory holes (Fig. 7A: 701), the at least one drain-side select gate transistor of each of the memory holes is coupled to one of a plurality of bit lines (Fig. 6: BL0/BL1) and the source-side select gate transistor of each of the memory holes is connected to a source line (see col. 13, ll. 31-39), the memory cells are grouped into a plurality of sub-blocks arranged vertically in the stack (Fig. 7A: SB0-3), the program operation is a reverse order program operation (see col. 17, ll. 28-37), and the control means is further configured to program the memory cells in the reverse order program operation beginning with the memory cells connected to one of the plurality of word lines adjacent a top of the stack and continuing vertically downward through the stack (see col. 17, ll. 28-37).
Regarding claim 3, Chen discloses wherein the control means is further configured, during in the pre-charge phase of the program operation, to apply the hole pre-charge voltage to each of the plurality of bit lines connected to the memory holed including the memory cells being programmed (see col. 21, ll. 58-67 and col. 22, ll. 1-2).
Regarding independent claim 8, Chen discloses a controller (Fig. 1A: 110, 122, 124, 128 and 132) in communication with a memory apparatus (Fig. 1A: 126) including memory cells (Fig. 7A) each connected to one of a plurality of word lines (Fig. 7A: WLs) and configured to retain a threshold voltage corresponding to one of a plurality of data states (see col. 19, ll. 12-27), the memory cells disposed in memory holes defining channels (see col. 14, ll. 9-36), the controller configured to:
generate holes by instructing the memory apparatus to apply a hole pre-charge voltage to the channels of the memory holes in a pre-charge phase of a program operation of the memory cells in the memory holes (see Abstract); and
following the pre-charge phase, instruct the memory apparatus to apply one of a series of programming pulses of a program voltage to selected ones of the plurality of word lines to program the memory cells connected thereto (Fig. 11: step 1105, see also Fig. 13A).
Regarding claim 9, Chen discloses wherein the plurality of word lines and a plurality of dielectric layers extend horizontally and overlay one another in an alternating fashion in a stack (see col. 2, ll. 44-52), the memory holes extend vertically through the stack (see col. 2, ll. 44-58, see also Fig. 6), the memory cells are connected in series between at least one drain-side select gate transistor on a drain-side of each of the memory holes (Fig. 7A: 716) and a source-side select gate transistor on a source-side of each of the memory holes (Fig. 7A: 701), the at least one drain-side select gate transistor of each of the memory holes is coupled to one of a plurality of bit lines (Fig. 6: BL0/BL1) and the source-side select gate transistor of each of the memory holes is connected to a source line (see col. 13, ll. 31-39), the memory cells are grouped into a plurality of sub-blocks arranged vertically in the stack (Fig. 7A: SB0-3), the program operation is a reverse order program operation (see col. 17, ll. 28-37), and the controller is further configured to instruct the memory apparatus to program the memory cells in the reverse order program operation beginning with the memory cells connected to one of the plurality of word lines adjacent a top of the stack and continuing vertically downward through the stack (see col. 17, ll. 28-37).
Regarding claim 10, Chen discloses wherein the controller is further configured, during in the pre-charge phase of the program operation, to instruct the memory apparatus to apply the hole pre-charge voltage to each of the plurality of bit lines connected to the memory holed including the memory cells being programmed (see col. 21, ll. 58-67 and col. 22, ll. 1-2).
Regarding independent claim 14, Chen discloses a method of operating a memory apparatus (Fig. 1A) including memory cells (Fig. 7A) each connected to one of a plurality of word lines (Fig. 7A: WLs) and configured to retain a threshold voltage corresponding to one of a plurality of data states (see col. 19, ll. 12-27), the memory cells disposed in memory holes defining channels (see col. 14, ll. 9-36), the method comprising the steps of:
generating holes by applying a hole pre-charge voltage to the channels of the memory holes in a pre-charge phase of a program operation of the memory cells in the memory holes (see Abstract); and
following the pre-charge phase, applying one of a series of programming pulses of a program voltage to selected ones of the plurality of word lines to program the memory cells connected thereto (Fig. 11: step 1105, see also Fig. 13A).
Regarding claim 15, Chen discloses wherein the plurality of word lines and a plurality of dielectric layers extend horizontally and overlay one another in an alternating fashion in a stack (see col. 2, ll. 44-52), the memory holes extend vertically through the stack (see col. 2, ll. 44-58, see also Fig. 6), the memory cells are connected in series between at least one drain-side select gate transistor on a drain-side of each of the memory holes (Fig. 7A: 716) and a source-side select gate transistor on a source-side of each of the memory holes (Fig. 7A: 701), the at least one drain-side select gate transistor of each of the memory holes is coupled to one of a plurality of bit lines (Fig. 6: BL0/BL1) and the source-side select gate transistor of each of the memory holes is connected to a source line (see col. 13, ll. 31-39), the memory cells are grouped into a plurality of sub-blocks arranged vertically in the stack (Fig. 7A: SB0-3), the program operation is a reverse order program operation (see col. 17, ll. 28-37), and the method further includes the step of programming the memory cells in the reverse order program operation beginning with the memory cells connected to one of the plurality of word lines adjacent a top of the stack and continuing vertically downward through the stack (see col. 17, ll. 28-37).
Regarding claim 16, Chen discloses further including during in the pre-charge phase of the program operation, to apply the hole pre-charge voltage to each of the plurality of bit lines connected to the memory holed including the memory cells being programmed (see col. 21, ll. 58-67 and col. 22, ll. 1-2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-6, 11-12 and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (U.S. 10,957,394; hereinafter “Chen”) in view of Suzuki et al. (U.S. 2022/0238167; hereinafter “Suzuki”).
Regarding claim 4, Chen discloses the limitations with respect to claim 3.
Furthermore, Chen teaches local interconnect extending vertically along the stack and connecting to the source line (see col. 12, ll. 35-41), the memory apparatus including a charge pump coupled to the plurality of bit lines and configured to supply the hole pre-charge voltage (see col. 12, ll. 42-56), the memory apparatus including pump disconnect transistors each coupled between the charge pump and the local interconnect and configured to selectively connect the charge pump to and disconnect the charge pump from the local interconnect (Fig. 2: 56, 173 and Fig. 3: 350), and wherein the control means is further configured to:
control the pump disconnect transistors to connect the charge pump to the local interconnect during an erase operation (see col. 11, ll. 66-67 and col. 12, ll. 1-8).
However, Chen is silent with respect to control the pump disconnect transistors to disconnect the charge pump from the local interconnect during the program operation.
Suzuki teaches control the pump disconnect transistors to disconnect the charge pump from the local interconnect during the program operation (see page 11, par. 0235).
Since Suzuki and Chen are from the same field of endeavor, the teachings described by Suzuki would have been recognized in the pertinent art of Chen.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Suzuki with the teachings of Chen for the purpose of enables efficient voltage generation, see Suzuki’s page 11, par. 0235.
Regarding claim 5, Chen in combination with Suzuki teaches the limitations with respect to claim 4.
Furthermore, Chen teaches wherein one of the plurality of sub-blocks comprise one of a plurality of blocks and ones of the plurality of blocks comprise one of a plurality of planes, and one of the pump disconnect transistors is used for each one of the plurality of planes (see col. 11, ll. 40-59).
Regarding claim 6, Chen in combination with Suzuki teaches the limitations with respect to claim 4.
Furthermore, Chen teaches wherein ones of the plurality of sub-blocks comprise one of a plurality of blocks, and one of the pump disconnect transistors is used for each one of the plurality of blocks (see col. 11, ll. 40-59).
Regarding claim 11, Chen discloses the limitations with respect to claim 10.
Furthermore, Chen teaches local interconnect extending vertically along the stack and connecting to the source line (see col. 12, ll. 35-41), the memory apparatus includes a charge pump coupled to the plurality of bit lines and configured to supply the hole pre-charge voltage (see col. 12, ll. 42-56), the memory apparatus including pump disconnect transistors each coupled between the charge pump and the local interconnect and configured to selectively connect the charge pump to and disconnect the charge pump from the local interconnect (Fig. 2: 56, 173 and Fig. 3: 350), and wherein the controller is further configured to:
instruct the memory apparatus to control the pump disconnect transistors to connect the charge pump to the local interconnect during an erase operation (see col. 11, ll. 66-67 and col. 12, ll. 1-8).
However, Chen is silent with respect to control the pump disconnect transistors to disconnect the charge pump from the local interconnect during the program operation.
Suzuki teaches control the pump disconnect transistors to disconnect the charge pump from the local interconnect during the program operation (see page 11, par. 0235).
Since Suzuki and Chen are from the same field of endeavor, the teachings described by Suzuki would have been recognized in the pertinent art of Chen.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Suzuki with the teachings of Chen for the purpose of enables efficient voltage generation, see Suzuki’s page 11, par. 0235.
Regarding claim 12, Chen in combination with Suzuki teaches the limitations with respect to claim 11.
Furthermore, Chen teaches wherein one of the plurality of sub-blocks comprise one of a plurality of blocks and ones of the plurality of blocks comprise one of a plurality of planes, and one of the pump disconnect transistors is used for each one of the plurality of planes (see col. 11, ll. 40-59).
Regarding claim 17, Chen discloses the limitations with respect to claim 16.
Furthermore, Chen teaches local interconnect extending vertically along the stack and connecting to the source line (see col. 12, ll. 35-41), the memory apparatus includes a charge pump coupled to the plurality of bit lines and configured to supply the hole pre-charge voltage (see col. 12, ll. 42-56), the memory apparatus includes pump disconnect transistors each coupled between the charge pump and the local interconnect and configured to selectively connect the charge pump to and disconnect the charge pump from the local interconnect (Fig. 2: 56, 173 and Fig. 3: 350), and the method further includes the steps of:
controlling the pump disconnect transistors to connect the charge pump to the local interconnect during an erase operation (see col. 11, ll. 66-67 and col. 12, ll. 1-8).
However, Chen is silent with respect to controlling the pump disconnect transistors to disconnect the charge pump from the local interconnect during the program operation.
Suzuki teaches controlling the pump disconnect transistors to disconnect the charge pump from the local interconnect during the program operation (see page 11, par. 0235).
Since Suzuki and Chen are from the same field of endeavor, the teachings described by Suzuki would have been recognized in the pertinent art of Chen.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Suzuki with the teachings of Chen for the purpose of enables efficient voltage generation, see Suzuki’s page 11, par. 0235.
Regarding claim 18, Chen in combination with Suzuki teaches the limitations with respect to claim 17.
Furthermore, Chen teaches wherein one of the plurality of sub-blocks comprise one of a plurality of blocks and ones of the plurality of blocks comprise one of a plurality of planes, and one of the pump disconnect transistors is used for each one of the plurality of planes (see col. 11, ll. 40-59).
Regarding claim 19, Chen in combination with Suzuki teaches the limitations with respect to claim 17.
Furthermore, Chen teaches wherein ones of the plurality of sub-blocks comprise one of a plurality of blocks, and one of the pump disconnect transistors is used for each one of the plurality of blocks (see col. 11, ll. 40-59).
Allowable Subject Matter
Claims 7, 13 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 7, there is no teaching or suggestion in the prior art of record to provide the recited the at least one drain-side select gate transistor includes a top drain-side select gate transistor and one or more other drain-side select gate transistors disposed vertically below the top drain-side select gate transistor and the control means is further configured, during the pre-charge phase of the program operation, to: apply a select gate pre-charge voltage to the one or more other drain-side select gate transistors of the memory holes including the memory cells being programmed; apply the select gate pre-charge voltage to the one or more other drain-side select gate transistors of the memory holes including the memory cells not being programmed; apply a steady state voltage to the selected ones of the plurality of word lines; apply the steady state voltage to unselected ones of the plurality of word lines; apply the hole pre-charge voltage to each of the plurality of bit lines connected to the memory holes including the memory cells not being programmed; apply a negative select gate voltage to the top drain-side select gate transistor; and apply the steady state voltage to the pump disconnect transistors.
With respect to claim 13, there is no teaching or suggestion in the prior art of record to provide the recited the at least one drain-side select gate transistor includes a top drain-side select gate transistor and one or more other drain-side select gate transistors disposed vertically below the top drain-side select gate transistor and the controller is further configured, during the pre-charge phase of the program operation, to: instruct the memory apparatus to apply a select gate pre-charge voltage to the one or more other drain-side select gate transistors of the memory holes including the memory cells being programmed; instruct the memory apparatus to apply the select gate pre-charge voltage to the one or more other drain-side select gate transistors of the memory holes including the memory cells not being programmed; instruct the memory apparatus to apply a steady state voltage to the selected ones of the plurality of word lines; instruct the memory apparatus to apply the steady state voltage to unselected ones of the plurality of word lines; instruct the memory apparatus to apply the hole pre-charge voltage to each of the plurality of bit lines connected to the memory holes including the memory cells not being programmed; instruct the memory apparatus to apply a negative select gate voltage to the top drain-side select gate transistor; and instruct the memory apparatus to apply the steady state voltage to the pump disconnect transistors.
With respect to claim 20, there is no teaching or suggestion in the prior art of record to provide the recited the at least one drain-side select gate transistor includes a top drain-side select gate transistor and one or more other drain-side select gate transistors disposed vertically below the top drain-side select gate transistor and the method, during the pre-charge phase of the program operation, includes the steps of: applying a select gate pre-charge voltage to the one or more other drain-side select gate transistors of the memory holes including the memory cells being programmed; applying the select gate pre-charge voltage to the one or more other drain-side select gate transistors of the memory holes including the memory cells not being programmed; applying a steady state voltage to the selected ones of the plurality of word lines; applying the steady state voltage to unselected ones of the plurality of word lines; applying the hole pre-charge voltage to each of the plurality of bit lines connected to the memory holes including the memory cells not being programmed; applying a negative select gate voltage to the top drain-side select gate transistor; and applying the steady state voltage to the pump disconnect transistors.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALFREDO BERMUDEZ LOZADA whose telephone number is (571)272-0877. The examiner can normally be reached 7:00AM-3:30PM EST.
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/Alfredo Bermudez Lozada/Primary Examiner, Art Unit 2825
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