DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
The previous drawing objection is withdrawn in light of the amended claims.
See the new rejections below of the amended claims.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: 4918. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 10-17, 20, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Hu, US 2020/0212229, in view of Edwards, US 2019/0229111 A1.
Claim 1: Hu discloses
a semiconductor substrate (104) including majority carrier dopants of a first conductivity type (N, [0013]);
a buried layer (PBL 106) in the semiconductor substrate and including majority carrier dopants of a second conductivity type (P);
a semiconductor layer (108 inside 121) disposed above the buried layer including majority carrier dopants of the second conductivity type;
an isolation structure, including:
a trench (131, lefthand one, FIG. 1) that extends through the semiconductor layer and into one of the semiconductor substrate and the buried layer,
a dielectric liner (133 and/or 134 and/or 135) that extends on a surface of the trench from the semiconductor layer to the one of the semiconductor substrate and the buried layer,
and polysilicon (126) including majority carrier dopants of the second conductivity type ([0017]), the polysilicon extends on the dielectric liner and fills the trench (the bottom of 118, FIG. 1);
and a field oxide structure (118) that extends on a portion of the semiconductor layer, a portion of the field oxide structure in contact with a portion of the isolation structure (FIG. 1).
PNG
media_image1.png
530
790
media_image1.png
Greyscale
Claim 1 also recites that “the dielectric liner is discontinuous at a bottom of the trench”, which Hu does not appear to disclose. The trench 121 of Hu is an isolation trench. “The metallization structure 154, 156 includes first conductive features 160, 162 of the metallization structure 154, 156 that connect the first polysilicon 126 to the first doped region 122. This provides an isolation trench structure 120 that electrically isolates the active region 110 of the semiconductor structure from the capacitor 130 and from other regions of the wafer or die 170.” [0028]. Thus Hu discloses isolation trenches 121 with a p-doped polysilicon center 126 connected to an n-doped region 122. Edwards discloses isolation trenches 258. “Cores 278 are formed on the silicon dioxide liners 276 in the deep trench 274 and the plurality of deep trenches 248. The cores 278 may include p-type polycrystalline silicon or other electrically conductive material. The cores 278 make electrical connections to the semiconductor material 260 below the n-type buried layer 266. The deep trench mask 286 is removed. The deep trench mask 286 may be removed prior to forming the cores 278 or after forming the cores 278.” Thus Edwards discloses isolation trenches 258 with a p-doped polysilicon center 278 connected to an n-doped region 266. Thus those in the art would expect that the isolation trench of Hu could be formed with contact at the bottom of the trench between the p-doped polysilicon 126 and the n-doped layer 122, either in addition to or instead of disclosed contact at the top, as Edwards teaches that this is a known way to form a functional isolation trench.
Claim 2: Hu discloses a doped region (136) including majority carrier dopants of the second conductivity type (P), the doped region extends from the semiconductor layer to the buried layer (FIG. 1).
PNG
media_image2.png
530
790
media_image2.png
Greyscale
Claim 3: the doped region is spaced apart from the isolation structure (FIG. 1).
Claim 4: Hu discloses a second doped region (126) including majority carrier dopants of the second conductivity type, wherein the second doped region extends from the semiconductor layer to the buried layer, and wherein the second doped region is spaced apart from the doped region, and the second doped region abuts a portion of the trench (FIG. 2).
Claim 5: the doped region abuts a portion of the trench (FIG. 1).
Claim 6: the trench extends through the semiconductor layer (bottom of 118) and through a portion of the field oxide structure (FIG. 1).
Claim 10: in Hu in view of Edwards, as explained above with respect to claim 1, the bottom of the trench abuts a doped region of the first conductivity type (the n-doped semiconductor).
Claim 11: the buried layer (106) laterally extends throughout the semiconductor substrate (FIG. 4).
Claim 12: Hu discloses
a substrate (104) of a first conductivity type (N, [0013]);
a buried layer (PBL 106) of a second conductivity type in the substrate;
a semiconductor layer (108) of the second conductivity type (P, [0013]) above the buried layer;
a first isolation structure, including:
a trench (121) that extends through the semiconductor layer and into the buried layer or the substrate,
a dielectric liner (133 and/or 134 and/or 135) disposed on a surface of the trench, wherein the dielectric liner is discontinuous at a bottom of the trench,
and polysilicon (126) disposed on the dielectric liner, wherein the polysilicon fills the trench;
and a second isolation structure (118) disposed at least partially over the semiconductor layer, a portion of the second isolation structure in contact with the first isolation structure (FIG. 1).
PNG
media_image1.png
530
790
media_image1.png
Greyscale
Claim 12 also recites that “the dielectric liner is discontinuous at a bottom of the trench”, which Hu does not appear to disclose. The trench 121 of Hu is an isolation trench. “The metallization structure 154, 156 includes first conductive features 160, 162 of the metallization structure 154, 156 that connect the first polysilicon 126 to the first doped region 122. This provides an isolation trench structure 120 that electrically isolates the active region 110 of the semiconductor structure from the capacitor 130 and from other regions of the wafer or die 170.” [0028]. Thus Hu discloses isolation trenches 121 with a p-doped polysilicon center 126 connected to an n-doped region 122. Edwards discloses isolation trenches 258. “Cores 278 are formed on the silicon dioxide liners 276 in the deep trench 274 and the plurality of deep trenches 248. The cores 278 may include p-type polycrystalline silicon or other electrically conductive material. The cores 278 make electrical connections to the semiconductor material 260 below the n-type buried layer 266. The deep trench mask 286 is removed. The deep trench mask 286 may be removed prior to forming the cores 278 or after forming the cores 278.” Thus Edwards discloses isolation trenches 258 with a p-doped polysilicon center 278 connected to an n-doped region 266. Thus those in the art would expect that the isolation trench of Hu could be formed with contact at the bottom of the trench between the p-doped polysilicon 126 and the n-doped layer 122, either in addition to or instead of disclosed contact at the top, as Edwards teaches that this is a known way to form a functional isolation trench.
Claim 13: a doped region (136 and/or 132) of the second conductivity type, the doped region extends (vertically) from the semiconductor layer to the buried layer (FIG. 1). Alternatively, Edwards discloses a doped region (180) of a conductivity type (N, [0040]) which is the same as the buried layer 166 (which would be the second conductivity type in Hu), the doped region extends from the semiconductor layer (160) to the buried layer (166). It would have been obvious to have used such a structure as a known effective transistor isolation structure.
Claim 14: the doped region is spaced apart from the first isolation structure (Hu FIG. 1).
Claim 15: Edwards discloses a second doped region (280) of a conductivity type (N, [0040]) the same as the buried layer 266 (which would be the second conductivity type in Hu), wherein the second doped region extends from the semiconductor layer (260) to the buried layer (266) and abuts a portion of the first isolation structure (274, FIG. 2C). It would have been obvious to have used such a structure as a known effective transistor isolation structure.
Claim 16: the doped region (Edwards 260) abuts a portion of the first isolation structure.
Claim 17: the trench extends through the semiconductor layer and through the second isolation structure (FIG. 1).
Claim 20: the buried layer laterally extends throughout the substrate (FIG. 4).
Claim 21: in Hu in view of Edwards, as explained above with respect to claim 1, the bottom of the trench abuts a doped region of the first conductivity type (the n-doped semiconductor).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Hu, US 2020/0212229, in view of Edwards and Sucher, US 2018/0342416 A1. Hu does not disclose the second isolation structure extends above the polysilicon. However, see Sucher, FIG. 5, isolation structure 275, formed so that it extends above the top of the substate 105. It would have been obvious to have formed such a isolation structure in Edwards as known in the art, in which case the top of isolation structure would be above the top of the polysilicon, which is at the level of the substrate (FIG. 1).
PNG
media_image3.png
314
756
media_image3.png
Greyscale
Allowable Subject Matter
Claims 7, 9 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The examiner did not find the claimed device, having an isolation structure with a polysilicon layer that extends higher than a field oxide on the top of the semiconductor layer, or the polysilicon layer extends above the substrate by a lower amount than the field oxide.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure and is listed in the attached Notice of References Cited.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER BRADFORD whose telephone number is (571)270-1596. The examiner can normally be reached 10:30-6:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469.295.9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PETER BRADFORD/Primary Examiner, Art Unit 2897
Prosecution Insights