Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) based on an application filed in the Republic of Korea on December 22, 2023, and receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. It should be noted that in order to effectively benefit from the foreign priority date, an English translation of the certified copy (of the foreign application as filed) filed together with a statement that the translation of the certified copy is accurate must be presented.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on July 18, 2024 was filed in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested:
--Semiconductor Package Including Dummy Patterns To Increase Heat Dissipation--
Claim Objections
Claim 1 is objected to because of the following informalities:
-“dummy patterns is exposed to the back surface” and “dummy patterns exposed to the back surface” should read --dummy patterns is exposed from the back surface-- and --dummy patterns exposed from the back surface--, respectively.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10, 12, 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (U.S. Pub. 2023/0078980), hereinafter Choi, in view of Chuang et al. (U.S. Pub. 2023/0369263), hereinafter Chuang. Examiner notes Choi was included within the IDS dated July 18, 2024.
Regarding Claim 1, Choi teaches a semiconductor package ((300); Figs. 1-3 and 17, Paragraph [0065]) comprising:
-a first semiconductor chip ((100); Figs. 1-3, Paragraph [0020]) including:
-a substrate ((110); Fig. 1, Paragraph [0021])) having a front surface (e.g. top of (110); Fig. 1) and a back surface (e.g. bottom of (110); Fig. 1), opposing each other,
-through-vias ((120); Fig. 1, Paragraph [0020]) that extend from the front surface (top of (110)) toward the back surface (bottom of (110)),
-dummy patterns ((210); Figs. 1-3, Paragraph [0026]) arranged around the through-vias (120) and such that at least one surface (e.g. top, away from substrate; Fig. 3) of each of the dummy patterns (210) is exposed (i.e. not covered by) from the back surface, a plurality of first back pads ((124) and corresponding (230) hereinafter (1BP); Fig. 3, Paragraph [0023]) arranged on the through-vias (120), and
-a plurality of second back pads ((212) and corresponding (230) hereinafter (2BP); Fig. 3, Paragraph [0027]) arranged on a first surface of the at least one surface of each of the dummy patterns (bottom of (210)) exposed from the back surface (bottom of (110)) (Examiner’s interpretation is that each of these second back pads may individually be on a separate dummy pattern, as all of the dummy patterns may share a same first surface. This interpretation will be unimportant following the incorporation of Chuang, which modifies Choi to a more direct variant of two or more second back structures directly contacting a single first surface of one of the dummy patterns as a consequence); and
-a second semiconductor chip (e.g. top chip (330) of Fig. 17, Paragraph [0065]) on the first semiconductor chip (e.g. bottom chip (320) corresponding to (100); Fig. 17, Paragraph [0065]), and including a plurality of first front pads (respective (124) and (230) of (330), hereinafter (1FP); Figs. 3 and 17) connected (via intervening conductive bump (342) and via (120)) to the plurality of first back pads (1BP), and a plurality of second front pads (respective (124) and (230) of (330), hereinafter (2FP); Figs. 3 and 17) connected (via intervening (350), (110), and thermal layers (220), (222), and (224) ;Examiner notes absent any limiting definition, the term “connected” does not exclude intervening layers) to each of the plurality of second back pads (2BP), wherein,
-when viewed in a plan view (e.g. in Fig. 2), the plurality of second back pads ((2BP) as part of (200)) are arranged in a first direction (e.g. lateral of Fig. 2) and a second direction (e.g. vertical of Fig. 2), perpendicular to the first direction,
Choi does not explicitly teach:
-wherein when viewed in the plan view, at least one of the dummy patterns overlaps two or more second back pads arranged in at least one direction of the first direction and the second direction among the plurality of second back pads.
Chuang teaches a semiconductor package ((500); Fig. 11, Paragraph [0045]) wherein:
-wherein when viewed in the plan view, at least one of the dummy patterns ((107), specifically embodiment (107c); Figs. 11 and 17, Paragraphs [0019] and [0042]) overlaps two or more second back pads ((316) by openings (1041); Figs. 11 and 17, Paragraphs [0045] and [0046]) arranged in at least one direction of the first direction (e.g. lateral of Fig. 17) and the second direction (e.g. vertical of Fig. 17) among the plurality of second back pads.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Chuang into the device of Choi such that when viewed in the plan view, at least one of the dummy patterns overlaps two or more second back pads arranged in at least one direction of the first direction and the second direction among the plurality of second back pads. This would be due to the fact that doing so would improve the heat dissipation efficiency (Chuang, Paragraph [0052]).
Regarding Claim 2, Choi as modified by Chuang teaches a semiconductor package (Choi, (300); Figs. 1-3 and 17, Paragraph [0065]) of Claim 1, wherein:
-the two or more second back pads (modified Choi, (2BP) corresponding to Chuang (316)) are in direct contact with the first surface of at least one dummy pattern (modified Choi, (210) corresponding to Chuang, (107)).
Regarding Claim 3, Choi as modified by Chuang teaches a semiconductor package (Choi, (300); Figs. 1-3 and 17, Paragraph [0065]) of Claim 1, wherein:
-the first semiconductor chip (modified Choi, (100)) further comprises a back protective layer (modified Choi, comprising sublayers (220) and (222); Fig. 3, Paragraph [0025]) on the back surface of the substrate (modified Choi, bottom of (110)), and surrounding at least a portion of each of the through-vias (modified Choi, (120)) and the dummy patterns (modified Choi, (210)), wherein
-the back protective layer includes a first protective layer (modified Choi, (220)) between the substrate (modified Choi, (110)) and the plurality of first back pads (modified Choi, (1BP)) and a second protective layer (modified Choi, (222)) between the substrate (modified Choi, (110)) and the dummy patterns (modified Choi, (210)).
Regarding Claim 4, Choi as modified by Chuang teaches a semiconductor package (Choi, (300); Figs. 1-3 and 17, Paragraph [0065]) of Claim 3, wherein:
-the through-vias (modified Choi, (120)) penetrate (i.e. go through) the first protective layer (modified Choi, (220)) and respectively contact the plurality of first back pads (modified Choi, (1BP)).
Regarding Claim 5, Choi as modified by Chuang teaches a semiconductor package (Choi, (300); Figs. 1-3 and 17, Paragraph [0065]) of Claim 3, wherein:
-the first surface of each of the dummy patterns (modified Choi, (210)) is coplanar with an upper surface of the first protective layer (modified Choi, bottom of (220), e.g. surface immediately adjacent to element (122)) and an uppermost surface of the second protective layer (modified Choi, bottom of (222)). (For clarity, Examiner notes “bottom” of Choi Figs. 1 and 3 is understood as the facing the top of the package, as compared to the orientation of Chuang Fig. 11)
Regarding Claim 6, Choi as modified by Chuang teaches a semiconductor package (Choi, (300); Figs. 1-3 and 17, Paragraph [0065]) of Claim 3, wherein:
-a thickness of the second protective layer (modified Choi, (222)) is equal to or less than a thickness of the first protective layer (modified Choi, (220)). (Choi, Paragraphs [0029] and [0030]- both described as having the same “relatively thin” thickness. See also Fig. 3)
Regarding Claim 8, Choi as modified by Chuang teaches a semiconductor package (Choi, (300); Figs. 1-3 and 17, Paragraph [0065]) of Claim 3, wherein:
-a thickness (e.g. along vertical of Choi, Fig. 3) of each of the dummy patterns (modified Choi, (210)) is greater than the thickness of the first protective layer (modified Choi, (220)).
Regarding Claim 10, Choi as modified by Chuang teaches a semiconductor package (Choi, (300); Figs. 1-3 and 17, Paragraph [0065]) of Claim 1, wherein:
-the first semiconductor chip (modified Choi, (100)) further comprises
-at least one functional pattern (modified Choi, (222) ‘functional’ as an insulator; Fig. 3, Paragraph [0030]) between (Choi, specifically between the lateral edges, e.g. Fig. 3) the plurality of first back pads (modified Choi, (1BP)) and the through-vias (modified Choi, (120)), and
-a back protective layer (modified Choi, (220); Fig. 3, Paragraph [0029]) surrounding at least a portion of each of the at least one functional pattern (modified Choi, (222)) and the dummy patterns (modified Choi, (210)), wherein
-the substrate (modified Choi (110)) has a first cavity (modified Choi, e.g. top leftmost (112) of Fig. 2; Figs. 2 and 3, Paragraph [0026]) in which the at least one functional pattern (modified Choi, (222)) is provided, and second cavities (Choi, e.g. the three (112)s vertically arranged on the center-left of Fig. 2) in which the dummy patterns (modified Choi, (210)) are provided, and
-the back protective layer (modified Choi, (220)) extends along the back surface of the substrate (modified Choi, (110)- See Paragraph [0029]), an inner surface of the first cavity, and an inner surface of each of the second cavities (necessarily, as it is present in all (200)).
Regarding Claim 12, Choi as modified by Chuang teaches a semiconductor package (Choi, (300); Figs. 1-3 and 17, Paragraph [0065]) of Claim 10, wherein:
-when viewed in the plan view (Choi, Fig. 2 or understandably as vertically in Fig. 3), the at least one functional pattern (modified Choi, (222)) overlaps two or more first back pads (modified, (1BP)s) arranged in at least one direction of the first direction (e.g. lateral in Figs. 2 and 3 of Choi) and the second direction (e.g. vertical of Fig. 2 of Choi) among the plurality of first back pads (necessarily as Fig. 3 is a cross-section and Fig. 2 shows repeated structural relations).
Regarding Claim 16, Choi as modified by Chuang teaches a semiconductor package (Choi, (300); Figs. 1-3 and 17, Paragraph [0065]) of Claim 10, wherein:
-a plurality of connection bumps (modified Choi, ((342); Fig. 17, Paragraph [0069]- See also Chuang Paragraph [0046]: e.g. wherein (314) represents two pillars and a solder ball between) electrically connecting the plurality of first front pads (modified Choi, (1FP)) and the plurality of first back pads (modified Choi, (1BP)) that correspond to each other, and electrically connecting the plurality of second front pads (modified Choi, (2FP)) and the plurality of second back pads (modified Choi, (2BP)) that correspond to each other; and
-an adhesive layer (Chaung, ‘underfill’; Paragraph [0047]- See also Choi, (350); Fig. 17, Paragraph [0070]) between the first semiconductor chip (modified Choi, (320) corresponding to (100)) and the second semiconductor chip (modified Choi, (330) / Chaung, (300)), the adhesive layer covering at least a portion of each of the plurality of connection bumps (modified Choi, (342) / Chaung, (314)).
Regarding Claim 17, Choi teaches a semiconductor package ((300); Figs. 1-3 and 17, Paragraph [0065]) comprising:
-a first semiconductor chip ((100); Figs. 1-3, Paragraph [0020]) including:
-a substrate ((110); Fig. 1, Paragraph [0021])) having a front surface (e.g. top of (110); Fig. 1) and a back surface (e.g. bottom of (110); Fig. 1) that oppose each other,
-a through-via ((120); Fig. 1, Paragraph [0020]) that extends from the front surface (top of (110)) toward the back surface (bottom of (110)),
-a dummy pattern ((210); Figs. 1-3, Paragraph [0026]) spaced apart from the through-via (120) and within a cavity that is recessed from the back surface toward the front surface ((112); Fig. 3, Paragraph [0021]),
-a back protective layer ((222); Fig. 3, Paragraph [0030]) between the substrate (110) and the dummy pattern (210),
-a first back pad ((124) and corresponding (230) hereinafter (1BP); Fig. 3, Paragraph [0023]) on the through-via (120)
-a second back pad ((212) and corresponding (230) hereinafter (2BP); Fig. 3, Paragraph [0027]) disposed on the dummy pattern (bottom of (210)) (Examiner notes Choi discloses a plurality of second back pads, but not on the dummy pattern), and
-a second semiconductor chip (e.g. top chip (330) of Fig. 17, Paragraph [0065]) on the first semiconductor chip (e.g. bottom chip (320) corresponding to (100); Fig. 17, Paragraph [0065]), and including a first front pad (respective (124) and (230) of (330), hereinafter (1FP); Figs. 3 and 17) and a plurality of second front pads (respective (124) and (230) of (330), hereinafter (2FP); Figs. 3 and 17) connected (via intervening (350), (110), and thermal layers (220), (222), and (224); Examiner notes absent any limiting definition, the term “connected” does not exclude intervening layers) to each of the plurality of second back pads (2BP), wherein,
-the first back pad (1BP) includes a first barrier layer ((230) of (1BP)) that is in contact with an upper surface of the through-via (120) (For clarity, Examiner notes “bottom” of Choi Figs. 1 and 3 is understood as the facing the top, thus the ‘upper’ surface of (120) is directly in contact with (230)), and a first conductor layer ((124) of (1BP)) on the first barrier layer ((230) of (1BP)), wherein
-a maximum width of the through-via (120) in a horizontal direction (e.g. lateral of Fig. 3) is less than a maximum width of the first back pad (1BP) in the horizonal direction (Fig. 3, See also Paragraph [0023]), wherein
-each of the plurality of second back pads (2BP) includes a second barrier layer ((230) of (2BP)) in contact with an upper surface of the dummy pattern (210) (As above, Examiner notes “bottom” of Choi Figs. 1 and 3 is understood as the facing the top), and a second conductor layer ((212) of (2BP)) on the second barrier layer ((230) of (2BP),
Choi does not explicitly teach:
-a plurality of second back pads disposed on the dummy pattern
- a width of the dummy pattern in the horizontal direction is greater than a sum of widths of each of the plurality of second back pads in the horizontal direction.
Chuang teaches a semiconductor package ((500); Fig. 11, Paragraph [0045]) wherein:
-a plurality of second back pads ((316) by openings (1041); Figs. 11 and 17, Paragraphs [0045] and [0046]) disposed on the dummy pattern ((107), e.g. embodiment (107c); Figs. 11 and 17, Paragraphs [0019] and [0042])
- wherein a width of the dummy pattern ((107)/(107C)) in the horizontal direction (e.g. lateral of Fig. 11 or Fig. 17) is greater than a sum of widths of each of the plurality of second back pads (316) in the horizontal direction.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Chuang into the device of Choi such that a plurality of second back pads disposed on the dummy pattern and a width of the dummy pattern in the horizontal direction is greater than a sum of widths of each of the plurality of second back pads in the horizontal direction. This would be due to the fact that doing so would improve the heat dissipation efficiency (Chuang, Paragraph [0052]).
Regarding Claim 18, Choi as modified by Chuang teaches a semiconductor package (Choi, (300); Figs. 1-3 and 17, Paragraph [0065]) of Claim 17, wherein:
-a upper surface of the through-via (modified Choi, (120)) and the upper surface of the dummy pattern (modified Choi, (210)) are coplanar. (As above, Examiner notes “bottom” of Choi Figs. 1 and 3 is understood as the facing the top of the package, as compared to the orientation of Chuang Fig. 11)
Regarding Claim 19, Choi as modified by Chuang teaches a semiconductor package (Choi, (300); Figs. 1-3 and 17, Paragraph [0065]) of Claim 17, wherein:
-the back protective layer (modified Choi, (222)) comprises at least one of silicon oxide and silicon nitride (Choi, ‘silicon nitride’; Paragraph [0030]).
Claims 7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Chuang and in further view of Ryu et al. (U.S. Pub. 2016/0148888), hereinafter Ryu.
Regarding Claim 7, Choi and Chuang teach the semiconductor package (Choi, (300); Figs. 1-3 and 17, Paragraph [0065]) according to Claim 6, but does not explicitly disclose:
-the thickness of the second protective layer is in a range of 1 μm to 2 µm.
Ryu teaches connection structures ((110); Figs. 1A-1F, Paragraph [0055]) for semiconductor packages (Paragraph [0003]) including a second protective layer ((32); Fig. 1B, Paragraph [0060]), wherein:
-the thickness of the second protective layer (32) is in a range of 1 μm to 2 µm (‘2 μm’; Paragraph [0061]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Yang into the device of Choi and Chuang such that the thickness of the second protective layer is in a range of 1 μm to 2 µm. This would be due to the fact that doing so would produce the predictable result of incorporating viable layer characteristics for the second protective layer and ensure desired device functionality.
Regarding Claim 9, Choi and Chuang teach the semiconductor package (Choi, (300); Figs. 1-3 and 17, Paragraph [0065]) according to Claim 8, but does not explicitly disclose:
-the thickness of each of the dummy patterns is in a range of 5 μm to 15 µm.
Ryu teaches connection structures ((110); Figs. 1A-1F, Paragraph [0055]) for semiconductor packages (Paragraph [0003]) including dummy patterns (e.g. (40); Fig. 1B, Paragraph [0067]), wherein:
-the thickness of each of the dummy patterns is in a range of 5 μm to 15 µm. (‘5 μm’; Paragraph [0067]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Yang into the device of Choi and Chuang such that the thickness of each of the dummy patterns is in a range of 5 μm to 15 µm. This would be due to the fact that doing so would produce the predictable result of incorporating viable layer characteristics for the dummy patterns and ensure desired device functionality.
Claims 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Chuang and in further view of Yang et al. (U.S. Pub. 2020/0365514), hereinafter Yang.
Regarding Claim 13, Choi and Chuang teach the semiconductor package (Choi, (300); Figs. 1-3 and 17, Paragraph [0065]) according to Claim 1, wherein:
-the second semiconductor chip (modified Choi, (330) / Chaung, (300)) further comprises an interconnection structure (‘redistribution structure’; Paragraph [0046]) that is electrically connected to the plurality of first front pads (modified Choi, (1FP) corresponding to Chuang (314); Paragraph [0045]),
- wherein when viewed in the plan view, the plurality of second front pads (modified Choi, (2FP), corresponding to Chuang, (316) by openings (1041); Figs. 11 and 17) are arranged in the first direction and the second direction (Chuang, e.g. vertical and lateral of Fig. 17),
Choi nor Chuang explicitly disclose the specific structure of the interconnection structure, thus do no not teach:
-the interconnection structure includes connection conductors adjacent to the plurality of second front pads,
-when viewed in the plan view, at least some of the connection conductors overlap two or more second front pads arranged in at least one direction of the first direction and the second direction among the plurality of second front pads.
Yang teaches a semiconductor package (e.g. (10G); Fig. 11, Paragraph [0066]), wherein:
-the interconnection structure (e.g. top (TS2); Fig. 11, Paragraph [0066]) includes connection conductors (top (222’) and (330); Fig. 11, Paragraphs [0030] and [0067]) adjacent to the plurality of second front pads (top (452); Fig. 11, Paragraph [0067]),
-when viewed in the plan view (e.g. viewed vertically in the cross-sectional view of Fig. 11), at least some of the connection conductors (top (222’) and (330)) overlap two or more second front pads (top (452)) arranged in at least one direction of the first direction and the second direction (in this case, explicitly in the lateral of Fig. 11) among the plurality of second front pads (top (452))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Yang into the device of Choi and Chuang such that the interconnection structure includes connection conductors adjacent to the plurality of second front pads and when viewed in the plan view, at least some of the connection conductors overlap two or more second front pads arranged in at least one direction of the first direction and the second direction among the plurality of second front pads. This would be due to the fact that doing so would incorporate an applicable interconnection structure, notably with improved routing feasibility, into the device (Yang, Paragraph [0067]).
Regarding Claim 14, Choi and Chuang as modified by Yang teaches a semiconductor package (Choi, (300); Figs. 1-3 and 17, Paragraph [0065]) of Claim 13, wherein:
-the two or more second front pads (modified Choi, (2FP), corresponding to Yang, top (452)) are electrically connected to an overlapping first connection conductor (Yang, top (330)) among the connection conductors, wherein
the two or more second back pads (modified Choi, (2BP), corresponding to Yang, bottom (452); Fig. 11) respectively connected to the two or more second front pads (modified Choi, (2FP) / Yang, top (452)) are electrically connected to a first dummy pattern of the plurality of dummy patterns (e.g. modified Choi (210), top left of Fig. 2 – See also Yang, bottom (330)), and wherein when viewed in the plan view, the first dummy pattern and the first connection conductor have a rectangular shape extending in the same direction (See, e.g. Yang, Fig. 11, parallel rectangles, also Chuang provides various patterns of various shapes, Paragraph [0038], and may match the below placed rectangular die, Paragraph [0023]). See also MPEP 2144.04 IV (B).
Regarding Claim 15, Choi and Chuang as modified by Yang teaches a semiconductor package (Choi, (300); Figs. 1-3 and 17, Paragraph [0065]) of Claim 13, wherein:
-the two or more second front pads (modified Choi, (2FP), corresponding to Yang, top (452)) are electrically insulated from (Yang Paragraphs [0030] and [0046]) an overlapping second connection conductor (Yang, e.g. top bottom-right most (222), connected to (254)) among the connection conductors, wherein
the two or more second back pads (modified Choi, (2BP), corresponding to Yang, bottom (452); Fig. 11) respectively connected to the two or more second front pads (modified Choi, (2FP) / Yang, top (452)) are electrically connected to a second dummy pattern of the plurality of dummy patterns (e.g. modified Choi (210), bottom left of Fig. 2 – See also Yang, bottom (330)), and wherein when viewed in the plan view, the second dummy pattern and the first connection conductor have different shapes (See, e.g. Yang, Fig. 11, different widths, see also Chuang provides different connector shapes, e.g. compare top down views in Figs. 13-17). See also MPEP 2144.04 IV (B).
Allowable Subject Matter
Claim 11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 20 is allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 11, the best prior art of record does not teach or fairly suggest, along with the other claimed features, which are necessary in informing the structure, a semiconductor package comprising:
-the back protective layer has an opening that exposes at least a portion of through-vias located within the first cavity,
-the at least one functional pattern is electrically connected to the through-via within the first cavity through the opening.
Regarding Claim 20, the best prior art of record does not teach or fairly suggest, along with the other claimed features, which are necessary in informing the structure, a semiconductor package comprising:
-a dummy pattern within a cavity that penetrates the first protective layer
-a second protective layer between an inner surface of the cavity and the dummy pattern
Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
U.S. Pub. 2016/0372436: Discloses a semiconductor package ((300); Fig. 13, Paragraph [0037]) comprising a first semiconductor chip ((10); Figs. 13, Paragraph [0035]) with through-vias (e.g. (38), (28), and (26); Fig. 13, Paragraphs [0018] and [0021]), dummy patterns ((38B); Fig. 13, Paragraph [0023]), a plurality of first back pads ((60); Fig. 13, Paragraph [0031]), a plurality of second back pads ((62); Fig. 13, Paragraph [0031]), and a second semiconductor chip ((200); Fig. 13, Paragraph [0035]) on the first semiconductor chip (10), among other limitations.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRI MIHALIOV whose telephone number is (571)270-5220. The examiner can normally be reached weekdays 7:30 - 17:30 US Eastern Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DMITRI MIHALIOV/ Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/ Supervisory Patent Examiner, Art Unit 2812
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