DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, filed 04/14/2026, with respect to claim(s) 1-20, have been considered but are not persuasive. Applicant argues that the combination of Cariello et al. (US 2020/0110660) and Uttarwar et al. (US 9,530,491) fails to teach or suggest: “selecting, based on the determined number of bits per memory cell, an error-handling operation of a plurality of error-handling operations.” However, Applicant’s argument is premised on an unduly narrow reading of the cited references and improperly attacks the references individually rather than the teachings of the combination as a whole. Cariello teaches suspending a copy-back operation, performing integrity checking on memory data, determining whether corruption exceeds a threshold, invoking error correction operations, and resuming the copy-back operation thereafter. See, e.g., paragraphs [0064]-[0076]. Uttarwar teaches memory systems employing different memory cell configurations including SLC, MLC, TLC, and QLC memory cells, each storing different numbers of bits per memory cell and having different operational and reliability characteristics. See, e.g., col. 1, ll. 23-33 and related discussion describing different programming and recovery operations associated with different memory cell densities. A person of ordinary skill in the art would have understood that different memory cell densities inherently require different error-management techniques because higher-density cells (e.g., TLC/QLC) exhibit narrower threshold margins and higher error susceptibility than lower-density cells (e.g., SLC). Accordingly, it would have been obvious to select an appropriate error-handling operation depending on the determined bits-per-cell configuration of the memory cells involved. Further, Cariello expressly teaches multiple possible error-handling operations, including ECC recovery, read-retry operations, and other correction mechanisms. See paragraphs [0034], [0075], and [0076]. Thus, the combined teachings reasonably suggest selecting among multiple error-handling operations depending on the identified memory-cell type and associated reliability characteristics. Applicant’s argument that neither reference expressly states the claimed selection operation is unpersuasive because obviousness under 35 U.S.C. §103 does not require an express textual disclosure of the precise claimed arrangement. Rather, the analysis considers what the combined teachings would have suggested to a person of ordinary skill in the art. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007).
Therefore, the combination of Cariello and Uttarwar teaches or at least suggests the disputed limitation, and the rejection of claims 1, 10, and 19 under 35 U.S.C. §103 is maintained.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Cariello et al (US2020/0110660 A1) (hereinafter D1) and further in view of US 9,530,491 B1 (hereinafter D2).
Claim 1: D1 teaches a system comprising: a memory device (e.g. item 110, fig. 1); and a processing device, operatively coupled to the memory device, to perform operations comprising: initiating a copyback operation to copy data from a first set of memory cells of the memory device to a second set of memory cells of the memory device (e.g. [0078]); suspending performing the copyback operation (e.g. Fig. 8, steps 850-860; [0035], [0089]); performing a data integrity check (e.g. dual-voltage read and comparison) on a subset of a memory to obtain a data integrity metric value (e.g. Fig. 7, steps 710-720; [0032], [0065]); responsive to determining that the data integrity metric value satisfies a threshold criterion, performing an error-handling operation on data stored on the third set of memory cells (e.g. Fig. 7, step 725; Fig. 8, step 860; [0034], [0065]); and resuming performing the copyback operation (e.g. Fig. 8, step, 850, 880, 890; [[0035], [0076]).
Not explicitly taught by D1 is:
Suspending copy-back due to a read command for a third set of memory cells;
Determining bits-per-cell configuration based on the integrity metric;
selecting, based on the determined number of bits per memory cell, an error- handling operation of a plurality of error-handling operations;
Performing the selected error-handling operation on data stored in the third set of memory cells;
However, D2 teaches a memory device that can store data in SLC mode as a backup while directly programming to MLC mode (col. 3, lines 10–25; Fig. 5). The system knows which cells are configured as SLC vs. MLC and uses this knowledge for error recovery. D2 also teaches that in the event of an MLC program failure, the system falls back to SLC-stored data and requests missing data from the host (col. 6, lines 20–35; Fig. 6). This demonstrates error-handling that is tailored to the memory cell configuration (SLC vs. MLC). Furthermore, D2 teaches memory systems employing different memory cell configurations including SLC, MLC, TLC, and QLC memory cells, each storing different numbers of bits per memory cell and having different operational and reliability characteristics. See, e.g., col. 1, ll. 23-33 and related discussion describing different programming and recovery operations associated with different memory cell densities. Finaly D2 acknowledges host data and prioritizes host interactions over internal programming (col. 5, lines 35–45). This establishes a motivation to suspend internal operations (like copy-back) when a higher-priority host read command arrives. Therefore, it would have been obvious to a POSITA, before the effective filing date of the claimed invention, to modify D1’s copy-back integrity management system to determine the bits-per-cell configuration of the memory cells involved and to select an appropriate error-handling operation based on that configuration, as taught by D2.
As per claims 10 and 19, the claimed features are rejected similarly to claim 1 above.
Claim 2: D1 and D2 teach the system of claim 1, but fail to teach that the error-handling operation does not use latch resources in response to the operations determining that the read command references a single-level cell (SLC) memory portion of the memory device. However, D1 teaches invoking error correction when integrity metric exceeds threshold, but does not specify latch usage and D2 teaches that SLC memory uses a simpler programming path and fewer latches than MLC/TLC. For example, SLC programming may use a single page latch, while MLC/TLC requires multiple page latches (col. 7, lines 15–25; Fig. 4). Therefore, it would have been obvious to a POSITA, before the effective filing date of the claimed invention, to design error-handling for SLC that does not use multiple latch resources, given that SLC has a simpler storage structure and D2 teaches latch resource differences between SLC and MLC. This is a routine design choice to optimize resource usage.
As per claims 11 and 20, the claimed features are rejected similarly to claim 2 above.
Claim 3: D1 and D2 teach the system of claim 1, but fail to teach the error-handling operation is selected, in response to the operations determining that the read command references a higher-level cell (HLC) memory portion of the memory device, from a set of error-handling operations that use latch resources and do not use latch resources. However, D1 teaches error correction invocation but does not teach selection based on cell type and D2 teaches that HLC (MLC/TLC) memory uses multiple latches and that error recovery may involve different latch-based and non-latch-based paths (e.g., using SLC backup data without full latch programming). Therefore, given that D2 teaches different recovery mechanisms for MLC/TLC that may or may not involve latch resources, and D1 teaches error-handling triggering, it would have been obvious to a POSITA, before the effective filing date of the claimed invention, to select an error-handling operation from a set of options (some using latches, some not) for HLC memory to optimize recovery efficiency.
As per claim 12, the claimed features are rejected similarly to claim 3 above.
Claim 4: D1 and D2 teach the system of claim 1, but fail to teach that the operations further comprise: responsive to determining that the error-handling operation fails to correct the data, performing a further error-handling operation on the data, wherein the further error-handling operation comprises an error-handling operation that uses latch resources. However, D1 teaches that if error correction is unsuccessful, the copy-back operation may be terminated (col. 17, lines 10–15; Fig. 8, step 890) and D2 teaches that if an MLC program fails, the system uses SLC backup data and latch resources to reprogram the data (col. 6, lines 20–35; Fig. 6). Therefore, it would have been obvious to a POSITA, before the effective filing date of the claimed invention, when initial error-handling fails, to employ a further error-handling operation that uses latch resources (such as reprogramming via latches) as taught by D2, since this is a known fallback recovery technique in memory systems.
As per claim 13, the claimed features are rejected similarly to claim 4 above.
Claim 5: D1 and D2 teach the system of claim 4, but fail to teach that the operations further comprise: responsive to determining that the further error-handling operation corrects the data, causing the memory device to copy the corrected data to a new destination set of memory cells of the memory device, wherein the new destination set of memory cells are configured to store the first number of bits per memory cell. However, D1 teaches storing corrected data to a destination location (Fig. 8, step 850) and D2 teaches reprogramming corrected data to MLC memory (col. 6, lines 30–35). It is common practice in memory management to relocate corrected data to a new physical location (e.g., for wear leveling or bad block avoidance). Therefore, given that D1 teaches storing corrected data and D2 teaches programming to MLC, it would have been obvious to a POSITA, before the effective filing date of the claimed invention, to copy the corrected data to a new destination set configured with the same bits-per-cell as the original data.
As per claim 14, the claimed features are rejected similarly to claim 5 above.
Claim 6: D1 and D2 teach the system of claim 4, but fail to teach the operations further comprise: responsive to determining that the further error-handling operation fails to correct the data; retiring the first set of memory cells of the memory device. However, retiring failing memory blocks (bad block management) is a well-known technique in NAND flash memory systems to maintain reliability. Given that both references deal with error recovery in flash memory, it would have been obvious to a POSITA, before the effective filing date of the claimed invention, to retire a memory cell set that cannot be corrected after multiple error-handling attempts, as this is a standard reliability measure.
As per claim 15, the claimed features are rejected similarly to claim 6 above.
Claim 7: D1 and D2 teach the system of claim 1, but fail to teach that the first set of memory cells are configured as SLC memory. However, D1 teaches that memory cells can be SLC or MLC (col. 1, lines 20–30) and D2 teaches that SLC memory is used for backup storage and can be configured separately from MLC (col. 3, lines 10–25). Therefore, it would have been obvious to a POSITA, before the effective filing date of the claimed invention, to use SLC memory as the source for a copy-back operation, as SLC is faster and more reliable, and D2 teaches using SLC for critical data backup.
As per claim 16, the claimed features are rejected similarly to claim 7 above.
Claim 8: D1 and D2 teach the system of claim 1, but fail to teach that the second set of memory cells are configured as HLC memory. However, D1 teaches that memory cells can be MLC (HLC) (col. 1, lines 20–30) and D2 teaches that MLC (HLC) memory is used for high-density storage (col. 2, lines 10–20). Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to use HLC memory as the destination for copy-back to increase storage density, as taught by D2, while D1 teaches copy-back to a destination address.
As per claim 17, the claimed features are rejected similarly to claim 8 above.
Claim 9: D1 and D2 teach the system of claim 1, but fail to teach that the data integrity metric value reflects at least one of a bit error count (BEC) value or a raw bit error rate (RBER) value. However, D1 teaches comparing two reads to determine a difference in bits (col. 12, lines 10–15). This difference is effectively a bit error count (BEC). RBER is a common derivative (bit error count divided by total bits). Expressing the integrity metric as BEC or RBER is a straightforward and conventional way to quantify errors in memory systems. Thus, a POSITA, before the effective filing date of the claimed invention, would have recognized that the bit difference metric taught by D1 is a form of BEC and could be expressed as RBER.
As per claim 18, the claimed features are rejected similarly to claim 9 above.
Conclusion
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/GUERRIER MERANT/Primary Examiner, Art Unit 2111 4/29/2026
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