DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 and 4-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shiu et al. (U.S. Patent No. 7,112,871).
Regarding to claim 1, Shiu teaches a semiconductor device comprising:
a lead including an obverse surface facing a first side in a thickness direction (Fig. 14, element 14/15, column 4, line 10, the top surface of the lead is the obverse surface);
a semiconductor element including a circuit section (Fig. 14, element 12, column 4, line 9), an element first surface facing the obverse surface in the thickness direction (Fig. 14, the bottom surface of integrated circuit 12), and a plurality of first electrodes provided on the element first surface, the plurality of first electrodes being connected to the obverse surface (Fig. 14, elements 44, column 6, line 30); and
a sealing resin covering a portion of the lead and the semiconductor element (Fig. 14, element 50, column 6, lines 62-63, column 7, lines 17-19); and
a first conductive section (Fig. 14, elements 46, column 7, line 9),
wherein the lead includes a plurality of first terminal sections aligned in a first direction perpendicular to the thickness direction (Fig. 14, element 15), and a second terminal section arranged closer to an end of the sealing resin in the first direction than are the plurality of first terminal sections (Fig. 14, element 14),
each of the plurality of first electrodes is electrically connected to the circuit section (Fig. 14, each first electrode 44 electrically connected to the circuit section of IC 12),
each of the plurality of first terminal sections is electrically connected to the circuit section via at least one of the plurality of first electrodes (Fig. 12, first terminal sections 15 is electrically connected to the circuit section of IC 12 via at least one of the plurality of first electrodes 44),
the first conductive section is interposed between the second terminal section and the element first surface and connected to the second terminal section and the element first surface (Fig. 14, the first conductive section 46 is interposed between the second terminal section 14 and the element first surface (bottom surface of IC 12) and connected to the second terminal section 14 and the element first surface (bottom surface of IC 12)), and
the first conductive section is insulated from the circuit section (Fig. 14, the first conductive section 46 is insulated from the circuit section of IC 12 by element 44, please note that the claim does not require electrical insulation).
Regarding to claim 2, Shiu teaches the lead includes two second terminal sections arranged on a first side and a second side in the first direction, respectively, relative to the plurality of first terminal sections (Fig. 14, element 14/left and element 14/right), and the semiconductor device further comprises two first conductive sections each arranged between one of the two second terminal sections and the element first surface (Fig. 14, element 46/left and element 46/right).
Regarding to claim 4, Shiu teaches each of the plurality of first terminal sections includes a first mounting surface facing a second side in the thickness direction, and a first side surface facing in a second direction perpendicular to the thickness direction and the first direction (Fig. 14, side surfaces of element 15), and the first mounting surface and the first side surface are exposed from the sealing resin (Fig. 14, top surface of element 15).
Regarding to claim 5, Shiu teaches the sealing resin includes a first resin side surface located at an end in the second direction and facing in the second direction, and the first side surface is flush with the first resin side surface, or is located inward of the sealing resin from the first resin side surface as viewed in the thickness direction (Fig. 14).
Regarding to claim 6, Shiu teaches the second terminal section includes a second mounting surface facing the second side in the thickness direction, a second side surface facing in the second direction, and a third side surface facing in the first direction, and the second mounting surface, the second side surface, and the third side surface are exposed from the sealing resin (Fig. 14, first and second side surfaces of second terminal section 14, and the third side surface (bottom surface) are exposed from the sealing resin).
Regarding to claim 7, Shiu teaches the sealing resin includes a second resin side surface located at an end in the first direction and facing in the first direction, the second side surface is flush with the first resin side surface, or is located inward of the sealing resin from the first resin side surface as viewed in the thickness direction, and the third side surface is flush with the second resin side surface, or is located inward of the sealing resin from the second resin side surface as viewed in the thickness direction (Fig. 14).
Regarding to claim 8, Shiu teaches the plurality of first electrodes are aligned in the first direction (Fig. 14).
Regarding to claim 9, Shiu teaches the first conductive section overlaps with the plurality of first electrodes as viewed in the first direction (Fig. 14).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-14 are rejected under 35 U.S.C. 103 as being unpatentable over Tsuji et al. (U.S. Patent No. 6,255,740) in view of Lee et al. (U.S. Patent No. 7,880,313).
Regarding to claim 1, Tsuji teaches a semiconductor device comprising:
a lead including an obverse surface facing a first side in a thickness direction (Fig. 18B, element 27/28, the top surface is the obverse surface);
a semiconductor element including a circuit section (Fig. 18B, element 41), an element first surface facing the obverse surface in the thickness direction (Fig. 18B, the bottom surface of semiconductor element 41), and a plurality of first electrodes provided on the element first surface, the plurality of first electrodes being connected to the obverse surface (Fig. 18B, elements 52/center below die 41); and
a sealing resin covering a portion of the lead and the semiconductor element (Fig. 18B, element 53, column 15, lines 26-29); and
a first conductive section (Fig. 18B, elements 52/right/left at the edge, not overlap die 41),
wherein the lead includes a plurality of first terminal sections aligned in a first direction perpendicular to the thickness direction (Fig. 18B, elements 28), and a second terminal section arranged closer to an end of the sealing resin in the first direction than are the plurality of first terminal sections (Fig. 18B, elements 27),
each of the plurality of first electrodes is connected to the circuit section (Fig. 18B, each first electrode 52/center connected to the circuit section of die 41),
each of the plurality of first terminal sections is connected to the circuit section via at least one of the plurality of first electrodes (Fig. 18B, first terminal sections 28 is connected to the circuit section of die 41 via at least one of the plurality of first electrodes 52/center),
the first conductive section is interposed between the second terminal section and the element first surface and connected to the second terminal section and the element first surface (Fig. 18B, the first conductive section 52/right/left is interposed between the second terminal section 27 and the element first surface (bottom surface of die 41) and connected to the second terminal section 27 and the element first surface (bottom surface of die 41)), and
the first conductive section is insulated from the circuit section (Fig. 18B).
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Tsuji does not clearly disclose the connections are electrical connections.
Lee discloses each of the plurality of first electrodes is electrically connected to the circuit section, first terminal section is electrically connected to the circuit section via
first electrodes (Fig. 4A). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Tsuji in view of Lee to configure electrical connections between the first terminal and the circuit section via the first electrodes, in order to provide control signals and power to operate the semiconductor element.
Regarding to claim 2, Tsuji teaches the lead includes two second terminal sections arranged on a first side and a second side in the first direction, respectively, relative to the plurality of first terminal sections (Fig. 18B, element 27/left and element 27/right), and the semiconductor device further comprises two first conductive sections each arranged between one of the two second terminal sections and the element first surface (Fig. 18B, element 52/left and element 52/right).
Regarding to claim 3, Tsuji teaches the semiconductor element includes a first wire electrically connected to the two first conductive sections (Fig. 18B, elements 43).
Regarding to claim 4, Tsuji teaches each of the plurality of first terminal sections includes a first mounting surface facing a second side in the thickness direction, and a first side surface facing in a second direction perpendicular to the thickness direction and the first direction (Fig. 18B, side surfaces of elements 28), and the first mounting surface and the first side surface are exposed from the sealing resin (Fig. 18B).
Regarding to claim 5, Tsuji teaches the sealing resin includes a first resin side surface located at an end in the second direction and facing in the second direction, and the first side surface is flush with the first resin side surface, or is located inward of the sealing resin from the first resin side surface as viewed in the thickness direction (Fig. 18B).
Regarding to claim 6, Tsuji teaches the second terminal section includes a second mounting surface facing the second side in the thickness direction, a second side surface facing in the second direction, and a third side surface facing in the first direction, and the second mounting surface, the second side surface, and the third side surface are exposed from the sealing resin (Fig. 18B, first and second side surfaces of second terminal section 27, and the third side surface (bottom surface) are exposed from the sealing resin).
Regarding to claim 7, Tsuji teaches the sealing resin includes a second resin side surface located at an end in the first direction and facing in the first direction, the second side surface is flush with the first resin side surface, or is located inward of the sealing resin from the first resin side surface as viewed in the thickness direction, and the third side surface is flush with the second resin side surface, or is located inward of the sealing resin from the second resin side surface as viewed in the thickness direction (Fig. 18B).
Regarding to claim 8, Tsuji teaches the plurality of first electrodes are aligned in the first direction (Fig. 18B).
Regarding to claim 9, Tsuji teaches the first conductive section overlaps with the plurality of first electrodes as viewed in the first direction (Fig. 18B).
Regarding to claim 10, Tsuji teaches the lead includes two second terminal sections arranged near a first side in the first direction relative to the plurality of first terminal sections (Fig. 18B, element 27/left and element 27/right), the semiconductor device further comprises two first conductive sections each arranged between one of the two second terminal sections and the element first surface (Fig. 18B, element 52/left and element 52/right), and the semiconductor element includes a second wire electrically connected to the two first conductive sections (Fig. 18B).
Regarding to claim 11, Tsuji teaches each of the plurality of first terminal sections includes a first mounting surface facing a second side in the thickness direction, and a first side surface facing in a second direction perpendicular to the thickness direction and the first direction, and the first mounting surface and the first side surface are exposed from the sealing resin (Fig. 14, surfaces of elements 28).
Regarding to claim 12, Tsuji teaches the sealing resin includes a first resin side surface located at an end in the second direction and facing in the second direction, and the first side surface is flush with the first resin side surface, or is located inward of the sealing resin from the first resin side surface as viewed in the thickness direction (Fig. 18B).
Regarding to claim 13, Tsuji teaches each of the second terminal sections includes a third mounting surface facing the second side in the thickness direction, and a fourth side surface facing in the first direction or the second direction, and the third mounting surface and the fourth side surface are exposed from the sealing resin (Fig. 14, surfaces of elements 27).
Regarding to claim 14, Tsuji teaches the sealing resin includes a second resin side surface located at an end in the first direction and facing in the first direction, and the fourth side surface is flush with one of the first resin side surface and the second resin side surface, or is located inward of the sealing resin from one of the first resin side surface and the second resin side surface as viewed in the thickness direction (Fig. 14, surfaces of element 53).
Pertinent Art
For the benefits of the Applicant, US-7732929-B2, US-6597059-B1, US-7335532-B2, US-7271470-B1, US-7612435-B2, US-7569920-B2, US-20060214308-A1, US-9006870-B2, US-10811342-B2, and US-9379048-B2, are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. These references fail to disclose “the first conductive section is interposed between the second terminal section and the element first surface and connected to the second terminal section and the element first surface, and the first conductive section is insulated from the circuit section.”
Conclusion
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/VU A VU/Primary Examiner, Art Unit 2897