Prosecution Insights
Last updated: October 27, 2026
Application No. 18/777,208

MULTI-LAYER CAPACITORS FOR THREE-DIMENSIONAL MEMORY SYSTEMS

Non-Final OA §102
Filed
Jul 18, 2024
Priority
Jul 25, 2023 — provisional 63/528,860
Examiner
MCCALL SHEPARD, SONYA D
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Micron Technology Inc.
OA Round
1 (Non-Final)
93%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 93% — above average
93%
Career Allowance Rate
1114 granted / 1200 resolved
+24.8% vs TC avg
Minimal +4% lift
Without
With
+3.5%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
36 currently pending
Career history
1234
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
49.8%
+9.8% vs TC avg
§102
33.5%
-6.5% vs TC avg
§112
13.6%
-26.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1200 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of claims 1-12 in the reply filed on 09/14/2026 is acknowledged. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ryu et al. US 2022/0013524. PNG media_image1.png 567 669 media_image1.png Greyscale Ryu et al. US 2022/0013524 Regarding claim 1, Ryu et al. in Fig. 5B and [0025]-[0095] disclose an apparatus, comprising: a cell selection transistor of a memory cell, the cell selection transistor comprising a channel CH [0037] extending along a first direction over a substrate LS; and a capacitor CAP of the memory cell coupled with the channel of the cell selection transistor and associated with an axis along the first direction over the substrate LS, the capacitor CAP comprising (annotated above): a first portion of a first electrode SN of the capacitor aligned along the axis; a first portion of a dielectric DE of the capacitor around the first portion of the first electrode SN about the axis; a first portion of a second electrode PN of the capacitor around the first portion of the dielectric about the axis; a second portion of the dielectric DE around the first portion of the second electrode PL/PN about the axis; a second portion of the first electrode SN around the second portion of the dielectric DE about the axis; a third portion of the dielectric DE around the second portion of the first electrode SN about the axis; and a second portion of the second electrode PN around the third portion of the dielectric DE about the axis. Regarding claim 2, Ryu et al. in Fig. 5B and [0025]-[0095] disclose the apparatus of claim 1, further comprising: a semiconductor material portion ACT [0037], a first portion of the semiconductor material portion comprising the channel CH of the cell selection transistor, and the first portion of the first electrode SN around a second portion SD2 of the semiconductor material portion ACT about the axis. Regarding claim 3, Ryu et al. in Fig. 5B and [0025]-[0095] disclose the apparatus of claim 2, wherein the first portion of the first electrode SN is in contact with the second portion SD2 of the semiconductor material portion ACT. Regarding claim 4, Ryu et al. in Fig. 5B and [0025]-[0095] disclose the apparatus of claim 2, wherein the first portion of the first electrode SN is contiguous (sharing a common border; touching; next or together in sequence) over an end of the second portion SD2 of the semiconductor material portion. Regarding claim 5, Ryu et al. in Fig. 5B and [0025]-[0095] disclose the apparatus of claim 1, wherein the first portion of the dielectric DE is contiguous (sharing a common border; touching; next or together in sequence) with the second portion of the dielectric DE over an end of the first portion of the second electrode PN along the first direction. Regarding claim 6, Ryu et al. in Fig. 5B and [0025]-[0095] disclose the apparatus of claim 1, wherein the second portion of the dielectric DE is contiguous (sharing a common border; touching; next or together in sequence) with the third portion of the dielectric DE over an end of the second portion of the first electrode SN along the first direction. Regarding claim 7, Ryu et al. in Fig. 5B and [0025]-[0095] disclose the apparatus of claim 1, wherein the first portion of the first electrode SN is contiguous (sharing a common border; touching; next or together in sequence) with the second portion of the first electrode SN over an end of the first portion of the dielectric DE along the first direction and over an end of the second portion of the dielectric DE along the first direction. Regarding claim 8, Ryu et al. in Fig. 5B and [0025]-[0095] disclose the apparatus of claim 7, wherein the first portion of the second electrode PN is contiguous (sharing a common border; touching; next or together in sequence) over an end of the first portion of the dielectric DE along the first direction and contiguous over an end of the first portion of the first electrode SN along the first direction. Regarding claim 9, Ryu et al. in Fig. 5B and [0025]-[0095] disclose the apparatus of claim 1, wherein the first portion of the second electrode PN is contiguous (sharing a common border; touching; next or together in sequence) with the second portion of the second electrode PN over an end of the second portion of the dielectric DE and over an end of the third portion of the dielectric DE. Regarding claim 10, Ryu et al. in Fig. 5B and [0025]-[0095] disclose the apparatus of claim 1, wherein the cell selection transistor further comprises a gate GAA comprising a first access line WL extending along a second direction over the substrate LS, and the cell selection transistor is coupled with a second access line BL extending along a third direction away from the substrate LS, Fig. 5A. Regarding claim 11, Ryu et al. in Fig. 5B and [0025]-[0095] disclose the apparatus of claim 1, wherein the cell selection transistor further comprises a gate GAA comprising a first access line WL extending along a second direction away from the substrate LS, and the cell selection transistor is coupled with a second access line BL extending along a third direction over the substrate LS, Fig. 5A. Regarding claim 12, Ryu et al. in Fig. 5B and [0025]-[0095] disclose the apparatus of claim 1, further comprising: a conductive plate PL in contact with the second electrode PN and extending along a second direction away from the substrate LS and a third direction over the substrate LS. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SONYA D MCCALL-SHEPARD whose telephone number is (571)272-9801. The examiner can normally be reached M-F: 8:30 AM-5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached at (571)272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Sonya McCall-Shepard/ Primary Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Jul 18, 2024
Application Filed
Sep 29, 2026
Non-Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
93%
Grant Probability
96%
With Interview (+3.5%)
2y 0m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1200 resolved cases by this examiner. Grant probability derived from career allowance rate.

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