DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the input circuit including a second transistor of the second type with a second gate terminal connected to the second enable signal and a second drain terminal coupled to the first node; a third transistor of the second type with a third gate terminal connected to the first enable signal and a third drain connected to the second source; and a fourth transistor of the second type with a fourth gate connected to the clock input signal, a fourth source connected to the supply voltage; and a fourth drain connected to the third source terminal must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 9 and 18 are objected to because of the following informalities:
In regards to claims 9 and 18, although it is evident that the input circuit has three separate transistors of the second type as illustrated in Fig 6A, there is nowhere that indicates that these transistors are connected in accordance with the claim language to include: the second transistor of the second type have a second gate receiving the second enable signal and a second drain coupled to the first node; the third transistor of the second type having a third gate terminal connected to the first enable signal and a third drain connected to the second source terminal; and a fourth transistor of the second type having a fourth gate terminal connected to the clock input signal, the fourth source terminal connected to the coupled to the voltage supply, and the fourth drain terminal connected to the third source terminal.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 7, 10-13, 15-16 and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tzeng et al. (US 2016/0147252).
In regards to claim 1, Tzeng discloses of a clock gating circuit comprising: an input circuit (comprised of 102, P2-P3, N2-N3, see Fig 1) coupled to a first node and a second node, and being configured to receive at least a first enable signal (for example Test_En) and a second enable signal (for example Ck_En), and to set a first control signal of the first node in response to at least the first enable signal (Test_En) or the second enable signal (Ck_En, see Fig 1); a cross-coupled pair of transistors (P4-P5) coupled between the first node and the second node, and being configured to receive at least the first control signal or a second control signal of the second node (see Fig 1); a first transistor of a first type (for example N4), the first transistor (N4) being coupled to the first node; a first pull-up transistor (for example P6) of a second type different from the first type (PMOS vs NMOS), the first pull-up transistor (P6) including a first gate terminal, a first drain terminal and a first source terminal, the first gate terminal being configured to receive a clock input signal (Ckin, Fin), the first drain terminal being coupled to at least the second node, and the first source terminal being coupled to a voltage supply (VDD), the first pull-up transistor (P6) being configured to adjust the second control signal responsive to the clock input signal (Ckin, Fin); and an output circuit (I2) coupled between the second node and an output node (Ckout, Fout), and configured to output an output clock signal (Ckout) in response to the second control signal (see Fig 1 and Paragraphs 0009-0029).
In regards to claim 2, Tzeng discloses of the clock gating circuit of claim 1, wherein the first transistor (N4) includes a second gate terminal, a second drain terminal and a second source terminal, the second gate terminal being configured to receive a third control signal inverted (via I1) from the first control signal, the second drain terminal being coupled to the first node and the cross-coupled pair of transistors (P4-P5), and the second source terminal being coupled to a third node (see Fig 1).
In regards to claim 3, Tzeng discloses of the clock gating circuit of claim 2, further comprising: a first inverter (I1) coupled between the first node and the second gate terminal (see Fig 1), and configured to generate the third control signal responsive to the first control signal (see Fig 1).
In regards to claim 4, Tzeng discloses of the clock gating circuit of claim 3, further comprising: a second transistor (N5) of the first type, the second transistor (N5) including a third gate terminal, a third drain terminal and a third source terminal, the third gate terminal being coupled to at least the first node, and configured to receive the first control signal, the third drain terminal being coupled to the second node and the cross-coupled pair of transistors (P4-P5), and the third source terminal being coupled to the third node and the second source terminal (see Fig 1).
In regards to claim 7, Tzeng discloses of the clock gating circuit of claim 1, the cross-coupled pair of transistors (P4-P5) comprises: a second transistor (P4) of the second type, the second transistor including a second gate terminal, a second drain terminal and a second source terminal, the second gate terminal being configured to receive the second control signal, and the second source terminal being coupled to the voltage supply (VDD); and a third transistor (P5) of the second type, the third transistor being configured to adjust the second control signal responsive to the first control signal, the third transistor including a third gate terminal, a third drain terminal and a third source terminal, the third gate terminal being configured to receive the first control signal, the third source terminal being coupled to the voltage supply (VDD), and the third drain terminal is coupled to the second node, wherein each of the second drain terminal, the third gate terminal, the first node and the first transistor are coupled together, and each of the third drain terminal, the second gate terminal and the second node are coupled together (see Fig 1).
In regards to claim 10, Tzeng discloses of a clock gating circuit comprising: an input circuit (comprised of 102, P2-P3, N2-N3) coupled to a first node and a second node, and being configured to receive at least a first enable signal (for example Test_En) and a second enable signal (for example Ck_En), and to set a first control signal of the first node in response to at least the first enable signal (Test_En) or the second enable signal (Ck_En); a cross-coupled pair of transistors (P4-P5) coupled between the first node and the second node, and being configured to receive at least the first control signal or a second control signal of the second node; a first transistor (N4) of a first type, the first transistor (N4) being coupled between the first node and a third node; a first pull-down transistor (N6) of the first type, the first pull-down transistor (N6) including a first gate terminal, a first drain terminal and a first source terminal, the first gate terminal being configured to receive a clock input signal (Ckin, Fin), the first drain terminal being coupled to at least the third node and the first transistor (N4), and the first source terminal being coupled to a reference voltage supply (GND), the first pull-down transistor (N6) being configured to adjust the second control signal responsive to the clock input signal (Ckin, Fin); and an output circuit (I2) coupled between the second node and an output node (Ckout, Fout), and configured to output an output clock signal (Ckout) in response to the second control signal (see Fig 1 and Paragraphs 0009-0029).
In regards to claim 11, Tzeng discloses of the clock gating circuit of claim 10, wherein the first transistor (N4) includes a second gate terminal, a second drain terminal and a second source terminal, the second gate terminal being configured to receive a third control signal inverted (via I1) from the first control signal, the second drain terminal being coupled to the first node and the cross-coupled pair of transistors (P4-P5), and the second source terminal being coupled to the third node and the first drain terminal (see Fig 1).
In regards to claim 12, Tzeng discloses of the clock gating circuit of claim 11, further comprising: a first inverter (I1) coupled between the first node and the second gate terminal, and configured to generate the third control signal responsive to the first control signal (see Fig 1).
In regards to claim 13, Tzeng discloses of the clock gating circuit of claim 12, further comprising: a second transistor (N5) of the first type, the second transistor including a third gate terminal, a third drain terminal and a third source terminal, the third gate terminal being coupled to at least the first node, and configured to receive the first control signal, the third drain terminal being coupled to the second node and the cross-coupled pair of transistors (P4-P5), and the third source terminal being coupled to the third node, the first drain terminal and the second source terminal (see Fig 1).
In regards to claim 15, Tzeng discloses of the clock gating circuit of claim 10, wherein the output circuit comprises: a first inverter (I2) coupled between the second node and the output node (Ckout, Fout), and configured to output the output clock signal (Ckout) in response to the second control signal (see Fig 1).
In regards to claim 16, Tzeng discloses of the clock gating circuit of claim 10, the cross-coupled pair of transistors (P4-P5) comprises: a second transistor (P4) of a second type different from the first type (PMOS vs NMOS), the second transistor (P4) including a second gate terminal, a second drain terminal and a second source terminal, the second gate terminal being configured to receive the second control signal, and the second source terminal being coupled to a voltage supply (VDD); and a third transistor (P5) of the second type, the third transistor being configured to adjust the second control signal responsive to the first control signal, the third transistor including a third gate terminal, a third drain terminal and a third source terminal, the third gate terminal being configured to receive the first control signal, the third source terminal being coupled to the voltage supply (VDD), and the third drain terminal is coupled to the second node, wherein each of the second drain terminal, the third gate terminal, the first node and the first transistor (N4) are coupled together, and each of the third drain terminal, the second gate terminal and the second node are coupled together (see Fig 1).
In regards to claim 19, Tzeng discloses of a method of operating a circuit, the method comprising: disabling a clock gating circuit (100) in response to at least a first enable signal (Test_En), a second enable signal (Ck_En) or a clock input signal (Ckin, Fin), wherein disabling the clock gating circuit comprises: generating a first control signal of a first node in response to at least the first enable signal (Test_En) or the second enable signal (Ck_En); generating a second control signal of a second node in response to at least the first control signal; enabling, by at least a first transistor, a first path between the first node and a reference voltage supply (GND) in response to a second control signal and the first enable signal (Test_En); disabling, by a second transistor, a second path between a third node and a fourth node in response to the first control signal; and setting, by a third transistor, the second control signal in response to at least the first control signal; and outputting, by an output circuit, an output clock signal in response to at least the second control signal; wherein a clock input signal (Ckin, Fin) does not correspond to the output clock signal (Ckout, see Fig 1).
In regards to claim 20, Tzeng discloses of the method of claim 19, wherein disabling the clock gating circuit (100) further comprises: setting, by a fourth transistor, the first control signal in response to at least the second control signal (see Fig 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-6 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Tzeng et al. (US 2016/0147252, hereafter Tzeng ‘252) in view of Tzeng et al. (US 216/0077544, hereafter Tzeng ‘544).
In regards to claims 5 and 14, Tzeng ‘252 discloses of the clock gating circuit of claims 4 and 13 as found within the respective explanations above, wherein the first inverter (I1) receives the first control signal and is coupled between the voltage supply (VDD) and the reference supply voltage (GND).
However, Tzeng ‘252 does not explicitly disclose of wherein the inverter comprises: a third transistor of the second type, the third transistor including a fourth gate terminal, a fourth drain terminal and a fourth source terminal, the fourth gate terminal being configured to receive the first control signal, the fourth drain terminal being coupled to at least the second gate terminal, and the fourth source terminal being coupled to the voltage supply; and a fourth transistor of the first type, the fourth transistor including a fifth gate terminal, a fifth drain terminal and a fifth source terminal, the fifth gate terminal being configured to receive the first control signal, the fifth drain terminal being coupled to the fourth drain terminal and the second gate terminal, the fifth source terminal being coupled to a reference voltage supply, and each of the fifth gate terminal, the fourth gate terminal, the first node and the third gate terminal being coupled together.
One of ordinary skill in the art readily recognizes that a convention inverter comprises a series connected PMOS transistor and NMOS transistor with their respective gate terminals connected together to receive an input signal, their respective drain terminals connected together at an output, the source of the PMOS connected to a supply and the source of the NMOS connected to a reference supply. However, to further illustrate this known configuration in the same endeavor of the invention, Tzeng ‘544 discloses of inverter (for example see 110, 112, 114, 122), wherein the inverter (114) comprises a series connected PMOS transistor and NMOS transistor with shared gate terminals and drain terminals, and where the source of the PMOS is connected to a supply voltage and the source of the NMOS is connected to a reference supply voltage (see Figs 1B, 2B).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have an inverter comprising a series connected PMOS and NMOS transistor as taught by Tzeng ’544 for utilizing well-known conventional integrated circuit designs for delivering an output signal that equates to the inverted input signal.
In regards to claim 6, Tzeng ‘252 in view of Tzeng ‘544 disclose of the clock gating circuit of claim 5, further comprising: a fifth transistor (N6 of Tzeng ‘252) of the first type, the fifth transistor including a sixth gate terminal, a sixth drain terminal and a sixth source terminal, the sixth gate terminal being configured to receive the clock input signal (Ckin, Fin), the sixth drain terminal being coupled to the second source terminal and the third node, and the sixth source terminal being coupled to the reference voltage supply (GND, see Tzeng ‘252 Fig 1).
Allowable Subject Matter
Claims 8 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
In regards to claim 8, the prior art does not disclose of nor render obvious the emphasized subject matter below, the clock gating circuit of claim 1, the input circuit comprises: a second transistor of the first type, the second transistor including a second gate terminal, a second drain terminal and a second source terminal, the second gate terminal being coupled to the second node, and configured to receive the second control signal, and the second drain terminal being coupled to at least the first node; a third transistor of the first type, the third transistor including a third gate terminal, a third drain terminal and a third source terminal, the third gate terminal being configured to receive the first enable signal, the third source terminal being coupled to a reference voltage supply; a fourth transistor of the first type, the fourth transistor including a fourth gate terminal, a fourth drain terminal and a fourth source terminal, the fourth gate terminal being configured to receive the second enable signal, the fourth source terminal being coupled to the reference voltage supply; wherein each of the second source terminal, the third drain terminal, and the fourth drain terminal are coupled together; and the second transistor and the third transistor are configured to adjust the first control signal responsive to the second control signal and the first enable signal, nor would it have been obvious to one of ordinary skill in the art to do so.
In regards to claim 17, the prior art does not disclose nor render obvious the emphasized subject matter below, the clock gating circuit of claim 10, the input circuit comprises: a second transistor of the first type, the second transistor including a second gate terminal, a second drain terminal and a second source terminal, the second gate terminal being coupled to the second node, and configured to receive the second control signal, and the second drain terminal being coupled to at least the first node; a third transistor of the first type, the third transistor including a third gate terminal, a third drain terminal and a third source terminal, the third gate terminal being configured to receive the first enable signal, the third source terminal being coupled to a reference voltage supply; a fourth transistor of the first type, the fourth transistor including a fourth gate terminal, a fourth drain terminal and a fourth source terminal, the fourth gate terminal being configured to receive the second enable signal, the fourth source terminal being coupled to the reference voltage supply; wherein each of the second source terminal, the third drain terminal, and the fourth drain terminal are coupled together; and the second transistor and the third transistor are configured to adjust the first control signal responsive to the second control signal and the first enable signal, nor would it have been obvious to one of ordinary skill in the art to do so.
Conclusion
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/JASON M CRAWFORD/Primary Examiner, Art Unit 2844