DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on December 5, 2025, has been entered.
Claims 1-4, 7-14, and 17-21 are pending in this office action and presented for examination. Claims 1-4, 7, 9-14, 17, and 19-21 are newly amended by the RCE received December 23, 2025.
Examiner notes that in claim 9, line 15, “a” appears to be newly added without appropriate underlining.
Drawings
The drawings are objected to because:
The amended drawings do not have satisfactory reproduction characteristics. (For example, compare the drawings filed December 5, 2025, in the file wrapper with the previously filed drawings in the file wrapper.)
The topmost instance of reference character 540 of amended FIG. 5 appears to be pointing solely to element 544, which does not appear to track with the specification’s description of element 540.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-4, 7-14, and 17-21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “a first compute engine of a plurality of compute engines” in lines 3-4. Claim 1 further recites the limitation “wherein the plurality of compute engines includes the first compute engine” in lines 11-12. However, it is unclear as to whether the latter limitation is intended to further narrow the former limitation, and if so, in what manner.
Claim 1 recites the limitation “to respective compute engine” in line 9. However, it is indefinite as to whether this limitation is to be interpreted as “to a respective compute engine” or “to respective compute engines”.
Claim 1 recites the limitation “writing, by the processor, first data to the first compute engine, the first data being used for a first output of a VMM of a vector and a matrix produced by a CIM circuit included in the first compute engine” in lines 14-16. However, the metes and bounds of this limitation are indefinite. For example, it is indefinite, in the context of the instant invention, as to whether the first data is the same as the recited vector and matrix, or distinct from the recited vector and matrix. For example, it is indefinite as to whether the first data is becoming a first output of the VMM, or whether the first data and the first output are input operands to a further calculation, or whether another interpretation is intended.
Claim 1 recites the limitation “a first output of a VMM of a vector and a matrix produced by a CIM circuit included in the first compute engine” in lines 15-16. However, the metes and bounds of this limitation is indefinite. For example, it is indefinite as to whether “produced by a CIM circuit included in the first compute engine” is limiting “a matrix” or “a first output”. For example, it is unclear as to whether the recited VMM is the same as, or different from, the VMM of the first compute engine conveyed via the limitation “a first compute engine of a plurality of compute engines … each compute engine of the plurality of compute engines including a corresponding compute-in-memory (CIM) circuit, the CIM circuit being configured to store a plurality of weights corresponding to a matrix and perform a vector-matrix multiplication (VMM) of a vector and the matrix using the matrix as an input, the plurality of weights, the matrix, and the vector corresponding to respective compute engine” in claim 1, lines 3-9. For example, it is unclear as to whether the recited vector is the same as, or different from, the vector of the first compute engine conveyed via the aforementioned limitation in claim 1, lines 3-9. For example, it is unclear as to whether the recited matrix is the same as, or different from, the matrix of the first compute engine conveyed via the aforementioned limitation in claim 1, lines 3-9. For example, it is unclear as to whether the recited CIM circuit is the same as, or different from, the CIM circuit of the first compute engine conveyed via the aforementioned limitation in claim 1, lines 3-9.
Claim 1 recites the limitation “the first output from the first compute engine” in lines 17-18. However, there is insufficient antecedent basis for this limitation in the claims.
Claim 1 recites the limitation “writing second data to the second compute engine by the processor, the second data being used for a second output of a VMM of a vector and a matrix produced by a CIM circuit included in the second compute engine” in lines 24-26. However, the metes and bounds of this limitation are indefinite. For example, it is indefinite, in the context of the instant invention, as to whether the second data is the same as the recited vector and matrix, or distinct from the recited vector and matrix. For example, it is indefinite as to whether the second data is becoming a second output of the VMM, or whether the second data and the second output are input operands to a further calculation, or whether another interpretation is intended.
Claim 1 recites the limitation “a second output of a VMM of a vector and a matrix produced by a CIM circuit included in the second compute engine” in lines 25-26. However, the metes and bounds of this limitation is indefinite. For example, it is indefinite as to whether “produced by a CIM circuit included in the second compute engine” is limiting “a matrix” or “a second output”. For example, it is unclear as to whether the recited VMM is the same as, or different from, the VMM of the second compute engine conveyed via the limitation “each compute engine of the plurality of compute engines including a corresponding compute-in-memory (CIM) circuit, the CIM circuit being configured to store a plurality of weights corresponding to a matrix and perform a vector-matrix multiplication (VMM) of a vector and the matrix using the matrix as an input, the plurality of weights, the matrix, and the vector corresponding to respective compute engine … wherein the plurality of compute engines includes … a second compute engine” in claim 1, lines 4-12. For example, it is unclear as to whether the recited vector is the same as, or different from, the vector of the second compute engine conveyed via the aforementioned limitation in claim 1, lines 4-12. For example, it is unclear as to whether the recited matrix is the same as, or different from, the matrix of the second compute engine conveyed via the aforementioned limitation in claim 1, lines 4-12. For example, it is unclear as to whether the recited CIM circuit is the same as, or different from, the CIM circuit of the second compute engine conveyed via the aforementioned limitation in claim 1, lines 4-12.
Claims 2-4, 7-8, and 21 are rejected for failing to alleviate the rejections of claim 1 above.
Claim 2 recites the limitation “The method of claim 1, wherein the method further comprises: identifying a first address range of the first compute engine” in lines 1-3. Claim 1, upon which claim 2 is dependent, recites the limitation “A method, comprising: executing, by a processor, an instruction identifying a first compute engine of a plurality of compute engines” in lines 2-4. However, it is indefinite, in the context of the instant invention, as to whether the recited identifying of claim 2 is elaborating on, or distinct from, the recited executing of claim 1.
Claim 2 recites the limitation “The method of claim 1, wherein the method further comprises: … writing the first data to the first address range of the first compute engine” in lines 1-6. Claim 1, upon which claim 2 is dependent, recites the limitation “writing, by the processor, first data to the first compute engine” in line 14. However, it is indefinite, in the context of the instant invention, as to whether the recited writing of claim 2 is elaborating on, or distinct from, the recited writing of claim 1.
Claims 3-4 are rejected for failing to alleviate the rejections of claim 2 above.
Claim 3 recites the limitation “a third address range” in line 4. However, it is unclear as to whether this limitation implicitly necessitates the metes and bounds of the claim to entail a second address range as well. For the purposes of this office action, Examiner is taking such to be the case. Note that the similar limitation “the third address range” is recited in claim 3, line 6, and claim 4, lines 4-5.
Claim 3 recites the limitation “loading third data from the third address range of the first compute engine, the third data being an output of a VMM of a vector and a matrix produced by the CIM circuit included in the first compute engine” in lines 6-8. However, it is indefinite as to whether the recited third data is the same as, or different from, “a first output” as recited in claim 1, line 15. Similarly, it is indefinite as to whether the recited output is the same as, or different from, “a first output” as recited in claim 1, line 15. Similarly, it is indefinite as to whether the recited VMM is the same as, or different from, “a VMM” as recited in claim 1, line 15. Similarly, it is indefinite as to whether the recited vector is the same as, or different from, “a vector” as recited in claim 1, line 15. Similarly, it is indefinite as to whether the recited matrix is the same as, or different from, “a matrix” as recited in claim 1, line 16. Note that “the third data” is further recited in claim 4, line 4, and claim 4, line 6.
Claim 3 recites the limitation “loading third data from the third address range of the first compute engine, the third data being an output of a VMM of a vector and a matrix produced by the CIM circuit included in the first compute engine” in lines 6-8. However, the metes and bounds of this limitation is indefinite. For example, it is indefinite as to whether “produced by the CIM circuit included in the first compute engine” is limiting “a matrix” or “an output”. For example, it is unclear as to whether the recited VMM is the same as, or different from, the VMM of the first compute engine conveyed via the limitation “a first compute engine of a plurality of compute engines … each compute engine of the plurality of compute engines including a corresponding compute-in-memory (CIM) circuit, the CIM circuit being configured to store a plurality of weights corresponding to a matrix and perform a vector-matrix multiplication (VMM) of a vector and the matrix using the matrix as an input, the plurality of weights, the matrix, and the vector corresponding to respective compute engine” as recited in claim 1, lines 3-9. For example, it is unclear as to whether the recited vector is the same as, or different from, the vector of the first compute engine conveyed via the aforementioned limitation in claim 1, lines 3-9. For example, it is unclear as to whether the recited matrix is the same as, or different from, the matrix of the first compute engine conveyed via the aforementioned limitation in claim 1, lines 3-9.
Claim 3 recites the limitation “the CIM circuit included in the first compute engine” in line 8. However, it is indefinite as to whether the antecedent basis for this limitation is the CIM circuit of the first compute engine conveyed via the limitation “a first compute engine of a plurality of compute engines … each compute engine of the plurality of compute engines including a corresponding compute-in-memory (CIM) circuit, the CIM circuit being configured to store a plurality of weights corresponding to a matrix and perform a vector-matrix multiplication (VMM) of a vector and the matrix using the matrix as an input, the plurality of weights, the matrix, and the vector corresponding to respective compute engine” as recited in claim 1, lines 3-9, or “a CIM circuit included in the first compute engine” as recited in claim 1, line 16.
Claim 4 is rejected for failing to alleviate the rejections of claim 3 above.
Claim 9 recites the limitation “a first compute engine of a plurality of compute engines” in lines 3-4. Claim 9 further recites the limitation “wherein the plurality of compute engines includes the first compute engine” in line 11. However, it is unclear as to whether the latter limitation is intended to further narrow the former limitation, and if so, in what manner.
Claim 9 recites the limitation “computer engine” in line 5. However, it is indefinite as to whether this computer engine is the same as, or different from, a compute engine as recited. For the purposes of this office action, Examiner is taking such to be the case.
Claim 9 recites the limitation “to respective compute engine” in lines 9-10. However, it is indefinite as to whether this limitation is to be interpreted as “to a respective compute engine” or “to respective compute engines”.
Claim 9 recites the limitation “writing first data to a first address range corresponding to the first compute engine by the processor, the first data being used for a first output of a VMM of a vector and a matrix produced by a CIM circuit included in the first compute engine” in lines 13-16. However, the metes and bounds of this limitation are indefinite. For example, it is indefinite, in the context of the instant invention, as to whether the first data is the same as the recited vector and matrix, or distinct from the recited vector and matrix. For example, it is indefinite as to whether the first data is becoming a first output of the VMM, or whether the first data and the first output are input operands to a further calculation, or whether another interpretation is intended.
Claim 9 recites the limitation “a first output of a VMM of a vector and a matrix produced by a CIM circuit included in the first compute engine” in lines 14-16. However, the metes and bounds of this limitation is indefinite. For example, it is indefinite as to whether “produced by a CIM circuit included in the first compute engine” is limiting “a matrix” or “a first output”. For example, it is unclear as to whether the recited VMM is the same as, or different from, the VMM of the first compute engine conveyed via the limitation “a first compute engine of a plurality of compute engines … each compute engine of the plurality of compute engines including a corresponding compute-in-memory (CIM) circuit, the CIM circuit being configured to store a plurality of weights corresponding to a matrix and perform a vector-matrix multiplication (VMM) of a vector and the matrix using the matrix as an input, the plurality of weights, the matrix, and the vector corresponding to respective compute engine” as recited in claim 9, lines 3-10. For example, it is unclear as to whether the recited vector is the same as, or different from, the vector of the first compute engine conveyed via the aforementioned limitation in claim 9, lines 3-10. For example, it is unclear as to whether the recited matrix is the same as, or different from, the matrix of the first compute engine conveyed via the aforementioned limitation in claim 9, lines 3-10. For example, it is unclear as to whether the recited CIM circuit is the same as, or different from, the CIM circuit of the first compute engine conveyed via the aforementioned limitation in claim 9, lines 3-10.
Claim 9 recites the limitation “a first address range corresponding to the first compute engine” in lines 13-14. However, it is indefinite as to whether this first address range is the same as, or different from, the first address range of the limitation “a first address range of a first compute engine” as recited in claim 9, lines 3-4.
Claim 9 recites the limitation “the first output from the first compute engine” in lines 17-18. However, there is insufficient antecedent basis for this limitation in the claims.
Claim 9 recites the limitation “the second address range corresponding to the second compute engine” in lines 23-24. However, there is insufficient antecedent basis for this limitation in the claims, and it is further unclear whether this limitation is intended to have antecedent basis back to “a second address range ‘for’ the second compute engine” as recited in claim 9, lines 21-22.
Claim 9 recites the limitation “writing, by the processor, second data to the second address range corresponding to the second compute engine, the second data being used for a second output of a VMM of a vector and a matrix produced by a CIM circuit included in the second compute engine” in lines 23-26. However, the metes and bounds of this limitation are indefinite. For example, it is indefinite, in the context of the instant invention, as to whether the second data is the same as the recited vector and matrix, or distinct from the recited vector and matrix. For example, it is indefinite as to whether the second data is becoming a second output of the VMM, or whether the second data and the second output are input operands to a further calculation, or whether another interpretation is intended.
Claim 9 recites the limitation “a second output of a VMM of a vector and a matrix produced by a CIM circuit included in the second compute engine” in lines 25-26. However, the metes and bounds of this limitation is indefinite. For example, it is indefinite as to whether “produced by a CIM circuit included in the second compute engine” is limiting “a matrix” or “a second output”. For example, it is unclear as to whether the recited VMM is the same as, or different from, the VMM of the second compute engine conveyed via the limitation “each compute engine of the plurality of compute engines including a corresponding compute-in-memory (CIM) circuit, the CIM circuit being configured to store a plurality of weights corresponding to a matrix and perform a vector-matrix multiplication (VMM) of a vector and the matrix using the matrix as an input, the plurality of weights, the matrix, and the vector corresponding to respective compute engine … wherein the plurality of compute engines includes … a second compute engine” as recited in claim 9, lines 5-12. For example, it is unclear as to whether the recited vector is the same as, or different from, the vector of the second compute engine conveyed via the aforementioned limitation in claim 9, lines 5-12. For example, it is unclear as to whether the recited matrix is the same as, or different from, the matrix of the second compute engine conveyed via the aforementioned limitation in claim 9, lines 5-12. For example, it is unclear as to whether the recited CIM circuit is the same as, or different from, the CIM circuit of the second compute engine conveyed via the aforementioned limitation in claim 9, lines 5-12.
Claim 9 recites the limitation “a third address range” in line 29. However, it is indefinite as to whether this third address range is the same as, or different from, “a third address range” as recited in claim 9, line 27.
Claim 9 recites the limitation “a third address range of the first compute engine” in line 31. However, it is indefinite as to whether this third address range is the same as, or different from, “a third address range for the first compute engine” as recited in claim 9, lines 27-28. Similarly, it is indefinite as to whether this third address range is the same as, or different from, “a third address range” as recited in claim 9, line 29.
Claim 9 recites the limitation “loading, by the processor, third data from a third address range, the third data being an output of a VMM of a vector and a matrix from a third address range of the first compute engine” in lines 29-31. However, it is indefinite as to whether the recited third data is the same as, or different from, “a first output” as recited in claim 9, line 14. Similarly, it is indefinite as to whether the recited output is the same as, or different from, “a first output” as recited in claim 9, line 14. Similarly, it is indefinite as to whether the recited VMM is the same as, or different from, “a VMM” as recited in claim 9, lines 14-15. Similarly, it is indefinite as to whether the recited vector is the same as, or different from, “a vector” as recited in claim 9, line 15. Similarly, it is indefinite as to whether the recited matrix is the same as, or different from, “a matrix” in claim 9, line 15. Note that the limitation “the third data” is further recited in claim 9, line 32.
Claim 9 recites the limitation “loading, by the processor, third data from a third address range, the third data being an output of a VMM of a vector and a matrix from a third address range of the first compute engine” in lines 29-31. However, the metes and bounds of this limitation is indefinite. For example, it is indefinite as to whether “from a third address range of the first compute engine” is limiting “a matrix” or “a first output”. For example, it is unclear as to whether the recited VMM is the same as, or different from, the VMM of the first compute engine conveyed via the limitation “a first compute engine of a plurality of compute engines … each compute engine of the plurality of compute engines including a corresponding compute-in-memory (CIM) circuit, the CIM circuit being configured to store a plurality of weights corresponding to a matrix and perform a vector-matrix multiplication (VMM) of a vector and the matrix using the matrix as an input, the plurality of weights, the matrix, and the vector corresponding to respective compute engine” as recited in claim 9, lines 3-10. For example, it is unclear as to whether the recited vector is the same as, or different from, the vector of the first compute engine conveyed via the aforementioned limitation in claim 9, lines 3-10. For example, it is unclear as to whether the recited matrix is the same as, or different from, the matrix of the first compute engine conveyed via the aforementioned limitation in claim 9, lines 3-10.
Claim 9 recites the limitation “the third data from the third address range of the first compute engine” in lines 32-33. However, there is insufficient antecedent basis for this limitation in the claims.
Claim 9 recites the limitation “applying … an activation function using a lookup table” in lines 32-33. However, it is indefinite, in the context of the inventive concept, whether the aforementioned applying is the same as, or different from, “applying” as recited in claim 9, line 17. Similarly, it is indefinite, in the context of the inventive concept, whether the aforementioned activation function is the same as, or different from, “an activation function” as recited in claim 9, line 17. Similarly, it is indefinite, in the context of the inventive concept, whether the aforementioned lookup table is the same as, or different from, “a lookup table” as recited in claim 9, line 19.
Claim 10 recites the limitation “computer engine” in line 2. However, it is indefinite as to whether this computer engine is the same as, or different from, a compute engine as recited. For the purposes of this office action, Examiner is taking such to be the case.
Claim 10 recites the limitation “the vector” in line 6. However, there is insufficient antecedent basis for this limitation in the claims.
Claim 10 recites the limitation “to respective compute engine” in lines 6-7. However, it is indefinite as to whether this limitation is to be interpreted as “to a respective compute engine” or “to respective compute engines”.
Claim 10 recites the limitation “write first data to the first compute engine, the first data being used for a first output of a VMM of a vector and a matrix produced by a CIM circuit included in the first compute engine” in lines 16-18. However, the metes and bounds of this limitation are indefinite. For example, it is indefinite, in the context of the instant invention, as to whether the first data is the same as the recited vector and matrix, or distinct from the recited vector and matrix. For example, it is indefinite as to whether the first data is becoming a first output of the VMM, or whether the first data and the first output are input operands to a further calculation, or whether another interpretation is intended.
Claim 10 recites the limitation “a first output of a VMM of a vector and a matrix produced by a CIM circuit included in the first compute engine” in lines 17-18. However, the metes and bounds of this limitation is indefinite. For example, it is indefinite as to whether “produced by a CIM circuit included in the first compute engine” is limiting “a matrix” or “a first output”. For example, it is unclear as to whether the recited VMM is the same as, or different from, the VMM of the first compute engine conveyed via the limitation “a plurality of compute engines, each computer engine of the plurality of compute engines including a corresponding compute-in-memory (CIM) circuit, the CIM circuit storing a plurality of weights corresponding to a matrix and configured to perform a vector-matrix multiplication (VMM) using the matrix as an input, the plurality of weights, the matrix, and the vector corresponding to respective compute engine … wherein the plurality of compute engines includes a first compute engine” in claim 10, lines 2-8. For example, it is unclear as to whether the recited vector is the same as, or different from, the vector of the first compute engine conveyed via the aforementioned limitation in claim 10, lines 2-8. For example, it is unclear as to whether the recited matrix is the same as, or different from, the matrix of the first compute engine conveyed via the aforementioned limitation in claim 10, lines 2-8. For example, it is unclear as to whether the recited CIM circuit is the same as, or different from, the CIM circuit of the first compute engine conveyed via the aforementioned limitation in claim 10, lines 2-8.
Claim 10 recites the limitation “the first output from the first compute engine” in lines 19-20. However, there is insufficient antecedent basis for this limitation in the claims.
Claim 10 recites the limitation “write second data to the second compute engine, the second data being used for a second output of a VMM of a vector and a matrix produced by a CIM circuit included in the second compute engine” in lines 25-27. However, the metes and bounds of this limitation are indefinite. For example, it is indefinite, in the context of the instant invention, as to whether the second data is the same as the recited vector and matrix, or distinct from the recited vector and matrix. For example, it is indefinite as to whether the second data is becoming a second output of the VMM, or whether the second data and the second output are input operands to a further calculation, or whether another interpretation is intended.
Claim 10 recites the limitation “a second output of a VMM of a vector and a matrix produced by a CIM circuit included in the second compute engine” in lines 26-27. However, the metes and bounds of this limitation is indefinite. For example, it is indefinite as to whether “produced by a CIM circuit included in the second compute engine” is limiting “a matrix” or “a second output”. For example, it is unclear as to whether the recited VMM is the same as, or different from, the VMM of the second compute engine conveyed via the limitation “a plurality of compute engines, each computer engine of the plurality of compute engines including a corresponding compute-in-memory (CIM) circuit, the CIM circuit storing a plurality of weights corresponding to a matrix and configured to perform a vector-matrix multiplication (VMM) using the matrix as an input, the plurality of weights, the matrix, and the vector corresponding to respective compute engine … wherein the plurality of compute engines includes … a second compute engine” in claim 10, lines 2-9. For example, it is unclear as to whether the recited vector is the same as, or different from, the vector of the second compute engine conveyed via the aforementioned limitation in claim 10, lines 2-9. For example, it is unclear as to whether the recited matrix is the same as, or different from, the matrix of the second compute engine conveyed via the aforementioned limitation in claim 10, lines 2-9. For example, it is unclear as to whether the recited CIM circuit is the same as, or different from, the CIM circuit of the second compute engine conveyed via the aforementioned limitation in claim 10, lines 2-9.
Claims 11-14 and 17-20 are rejected for failing to alleviate the rejections of claim 10 above.
Claim 11 recites the limitation “The compute tile of claim 10, wherein the processor is further configured to: identify a first address range of the first compute engine” in lines 1-3. Claim 10, upon which claim 11 is dependent, recites the limitation “the processor is configured to: identify the first compute engine of the plurality of compute engines” in lines 13-15. However, it is indefinite, in the context of the instant invention, as to whether the recited identifying of claim 11 is elaborating on, or distinct from, the recited executing of claim 10.
Claim 11 recites the limitation “The compute tile of claim 10, wherein the processor is further configured to: … write the first data to the first address range of the first compute engine” in lines 1-7. Claim 10, upon which claim 11 is dependent, recites the limitation “write first data to the first compute engine” in line 16. However, it is indefinite, in the context of the instant invention, as to whether the recited writing of claim 11 is elaborating on, or distinct from, the recited writing of claim 10.
Claim 12 recites the limitation “a third address range” in line 4. However, it is unclear as to whether this limitation implicitly necessitates the metes and bounds of the claim to entail a first address range and a second address range as well. For the purposes of this office action, Examiner is taking such to be the case. Note that the similar limitation “the third address range” is recited in claim 12, line 6.
Claim 12 recites the limitation “load third data from the third address range of the first compute engine, the third data being an output of a VMM of a vector and a matrix produced by the CIM circuit included in the first compute engine” in lines 6-8. However, it is indefinite as to whether the recited third data is the same as, or different from, “a first output” as recited in claim 10, lines 16-17. Similarly, it is indefinite as to whether the recited output is the same as, or different from, “a first output” as recited in claim 10, lines 16-17. Similarly, it is indefinite as to whether the recited VMM is the same as, or different from, “a VMM” as recited in claim 10, line 17. Similarly, it is indefinite as to whether the recited vector is the same as, or different from, “a vector” as recited in claim 10, line 17. Similarly, it is indefinite as to whether the recited matrix is the same as, or different from, “a matrix” as recited in claim 10, line 17. Note that “the third data” is further recited in claim 13, line 7; and claim 13, line 8.
Claim 12 recites the limitation “load third data from the third address range of the first compute engine, the third data being an output of a VMM of a vector and a matrix produced by the CIM circuit included in the first compute engine” in lines 6-8. However, the metes and bounds of this limitation is indefinite. For example, it is indefinite as to whether “produced by the CIM circuit included in the first compute engine” is limiting “a matrix” or “an output”. For example, it is unclear as to whether the recited VMM is the same as, or different from, the VMM of the first compute engine conveyed via the limitation “a plurality of compute engines, each computer engine of the plurality of compute engines including a corresponding compute-in-memory (CIM) circuit, the CIM circuit storing a plurality of weights corresponding to a matrix and configured to perform a vector-matrix multiplication (VMM) using the matrix as an input, the plurality of weights, the matrix, and the vector corresponding to respective compute engine … wherein the plurality of compute engines includes a first compute engine” as recited in claim 10, lines 2-8. For example, it is unclear as to whether the recited vector is the same as, or different from, the vector of the first compute engine conveyed via the aforementioned limitation in claim 10, lines 2-8. For example, it is unclear as to whether the recited matrix is the same as, or different from, the matrix of the first compute engine conveyed via the aforementioned limitation in claim 10, lines 2-8.
Claim 12 recites the limitation “the CIM circuit included in the first compute engine” in line 8. However, it is indefinite as to whether the antecedent basis for this limitation is the CIM circuit of the first compute engine conveyed via the limitation “a plurality of compute engines, each computer engine of the plurality of compute engines including a corresponding compute-in-memory (CIM) circuit, the CIM circuit storing a plurality of weights corresponding to a matrix and configured to perform a vector-matrix multiplication (VMM) using the matrix as an input, the plurality of weights, the matrix, and the vector corresponding to respective compute engine … wherein the plurality of compute engines includes a first compute engine” as recited in claim 10, lines 2-8, or “a CIM circuit included in the first compute engine” as recited in claim 10, lines 17-18.
Claims 13-14 are rejected for failing to alleviate the rejections of claim 12 above.
Claim 13 recites the limitation “wherein loading the third data from the first compute engine is performed in response to the polling indicating the third data is available for loading.” in lines 6-9. However, it is indefinite as to whether this limitation is intended to further limit the limitation “load third data from the third address range of the first compute engine” in claim 12, line 6, due to the lack of “the third address range of” in the aforementioned limitation of claim 13.
Claim 14 is rejected for failing to alleviate the rejection of claim 13 above.
Response to Arguments
Applicant on page 15 argues: "The Office objected to the Abstract for informalities. Office Action at page 2. Without conceding to the merits of the objection, in order to advance prosecution, Applicant amends the Abstract to address the Office's concerns. Accordingly, the objection to the Specification should be withdrawn."
In view of the aforementioned amendment, the previously presented objection to the abstract is withdrawn.
Applicant on page 15 argues: 'Applicant amends FIG. 3 and FIG. 5, and paragraph [0068] to address the Office's concerns. In particular, in FIG. 3, Applicant adds reference numeral "350" which is described in paragraph [0049] of the Specification. In FIG. 5, Applicant amends "Control Unit 540" to "Control Unit 520." Applicant also amends paragraph [0068] of the Specification to reflect the change of the reference numeral for the control unit in FIG. 5. The amendments are fully supported by the original drawings and specification. No new matter is added. Accordingly, the objection to the drawings should be withdrawn.'
In view of the aforementioned amendments, the previously presented objections to the drawings are withdrawn. However, Examiner notes that the amended drawings catalyze additional issues. For example, the amended drawings do not have satisfactory reproduction characteristics. (For example, compare the drawings filed December 5, 2025, in the file wrapper with the previously filed drawings in the file wrapper.) In addition, the topmost instance of reference character 540 of amended FIG. 5 appears to be pointing solely to element 544, which does not appear to track with the specification’s description of element 540.
Applicant across pages 15-16 argues: "The Office objected to claims 1-4, 7-14, and 17-21 for informalities. Office Action at pages 3-4. Applicant amends claims 1, 3, 9, and 10 to obviate the objection to the claims. Accordingly, the objection to claims 1-4, 7-14, and 17-21 should be withdrawn."
In view of the aforementioned amendments, the previously presented objections to the claims are withdrawn.
Applicant on page 16 argues: "The Office indicated that certain phrases in claims 1, 9, and 10 were interpreted to invoke the statutory construction provided under 35 U.S.C. § 112(f). Office Action at pages 4-7. Applicant disagrees that the previously presented claim language should be interpreted as invoking statutory construction. Nevertheless, without conceding to the merits of the interpretation, Applicant amends claims 1, 9, and 10 to clarify that the statutory construction is not invoked. Accordingly, Applicant respectfully requests that the Office clarify that the claims are no longer being interpreted under 35 U.S.C. § 112(f)."
In view of the aforementioned amendments, the previously presented claim interpretation under 35 U.S.C. § 112(f) is no longer applicable.
Applicant on page 16 argues: "The Office rejected claims 1-4, 7-14, and 17-21 under 35 U.S.C. § 112(a). Office Action at pages 7-10. Applicant amends claims 1, 9, and 10 to address the Office's concerns. Accordingly, the rejection of claims 1-4, 7-14, and 17-21 under 35 U.S.C. § 112(a) should be withdrawn."
In view of the aforementioned amendments, the previously presented rejections under 35 U.S.C. § 112(a) are withdrawn.
Applicant across pages 16-17 argues: "The Office rejected claims 1-4, 7-14, and 17-21 under 35 U.S.C. § 112(b). Office Action at pages 10-31. Applicant amends claims 1-4, 7, 9-14, 17, and 19-21 to address the Office's concerns. Accordingly, the rejection of claims 1-4, 7-14, and 17-21 under 35 U.S.C. § 112(b) should be withdrawn."
Various previously pending rejections of the claims under 35 U.S.C. §112(b) are withdrawn in view of the amendments to the claims. However, other previously presented rejections under 35 U.S.C. §112(b) remain applicable, and in various cases the amendments to the claims introduce additional indefinite subject matter; see the Claim Rejections - 35 USC § 112 section above.
Conclusion
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/KEITH E VICARY/Primary Examiner, Art Unit 2183
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