Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 – 5, 8, 10 – 14, 17, 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipate by Fillion (US 20190304910).
Regarding claim 1, Fillion discloses an applique (an electronics module 10, Fig. 1), comprising:
a substrate (an insulating substrate 24) having an adhesive property (the adhesive property of the substrate 24; paragraph 51); and
conductive gel (the macro-via 26), contained within openings (the openings on the substrate 24 for the via 26) in the substrate;
wherein the conductive gel is configured to electrically couple with a first electronic component (the components such as 28 and 14 on the surface of the substrate 24) and a second electronic component (component 12 on the bottom surface of the substrate 24) to electrically couple the first electronic component to the second electronic component;
wherein the adhesive property of the substrate is configured to adhere at least one of the first electronic component (28) and the second electronic component to the substrate (12).
Regarding claim 2, Fillion discloses the claimed invention as set forth in claim 1. Fillion further suggests the first electronic component includes a plurality of contacts (the junctions between the vias and the component and/or pads 18 and 34) and wherein the conductive gel is configured to electrically couple with each of the plurality of contacts (the vias electrically couple the component to another component).
Regarding claim 3, Fillion discloses the claimed invention as set forth in claim 2. Fillion further suggests the conductive gel forms a plurality of vias (26, 27A, 27B; Fig. 2), each of the plurality of vias configured to electrically couple to a different one of the plurality of contacts (each via 26 couples to a different junction of the component).
Regarding claim 4, Fillion discloses the claimed invention as set forth in claim 3. Fillion further suggests the plurality of vias extend through the substrate (the via 26 extends through the substrate 24).
Regarding claim 5, Fillion discloses the claimed invention as set forth in claim 4. Fillion further discloses second electronic component comprises a plurality of electrical contacts (the contacts corresponding to the vias of component 12, Fig. 2) and wherein each of the plurality of vias are configured to electrically couple to a different one of the plurality of electrical contacts (Fig. 2).
Regarding claim 8, Fillion discloses the claimed invention as set forth in claim 1. Fillion further suggests the substrate comprises an adhesive film (an adhesive layer can be applied on the surface of the substrate 24; paragraph 51) that provides the adhesive property.
Regarding claim 10, Fillion discloses a system, comprising:
a first electronic component (components 28, 14, Fig. 1);
a second electronic component (component 12); and
an applique, comprising: a substrate (substrate 24) having an adhesive property (the adhesive property of the substrate 24; paragraph 51); and
conductive gel (the via 26), contained within openings (the openings for the via 26) in the substrate;
wherein the conductive gel is configured to electrically couple with the first electronic component (28) and the second electronic component (12) to electrically couple the first electronic component to the second electronic component;
wherein the adhesive property of the substrate is configured to adhere at least one of the first electronic component and the second electronic component to the substrate (paragraph 51).
Regarding claim 11, Fillion discloses the claimed invention as set forth in claim 10. Fillion further discloses the first electronic component includes a plurality of contacts (the junctions between the vias and the component and/or pads 18 and 34) and wherein the conductive gel is configured to electrically couple with each of the plurality of contacts (the vias electrically couple the component to another component).
Regarding claim 12, Fillion discloses the claimed invention as set forth in claim 2. Fillion further suggests the conductive gel forms a plurality of vias (26, 27A, 27B; Fig. 2), each of the plurality of vias configured to electrically couple to a different one of the plurality of contacts (each via 26 couples to a different junction of the component).
Regarding claim 13, Fillion discloses the claimed invention as set forth in claim 12. Fillion further suggests the plurality of vias extend through the substrate (the via 26 extends through the substrate 24).
Regarding claim 14, Fillion discloses the claimed invention as set forth in claim 13. Fillion further discloses second electronic component comprises a plurality of electrical contacts (the contacts corresponding to the vias of component 12, Fig. 2) and wherein each of the plurality of vias are configured to electrically couple to a different one of the plurality of electrical contacts (Fig. 2).
Regarding claim 17, Fillion discloses the claimed invention as set forth in claim 10. Fillion further suggests the substrate comprises an adhesive film (an adhesive layer can be applied on the surface of the substrate 24; paragraph 51) that provides the adhesive property.
Regarding claim 20, Fillion discloses the claimed invention as set forth in claim 10. Fillion further suggests the first electronic component is a chip package (the component 12 is a semiconductor chip that may be considered as a first component. Component 14 is also a semiconductor chip).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 6, 7, 15, 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fillion (US 20190304910).
Regarding claim 6, Fillion discloses the claimed invention as set forth in claim 1.
Fillion does not explicitly disclose the substrate is comprised of a thermoplastic polyurethane.
Fillion suggests the substrate is made of polymer film or other suitable materials (paragraph 33).
It would have been obvious to one having skill in the art at the effective filing date of the invention to use one of the polymers such as thermoplastic polyurethane which is relatively common due to lower price compared to polyimide which is also being recommended by Fillion as an option when cost of the production may be a factor in choosing the material.
Regarding claim 7, Fillion discloses the claimed invention as set forth in claim 1.
Fillion does not explicitly disclose the substrate is comprised of at least one of: a thermoset epoxy-based film and a C-stage resin film.
Fillion suggests polymer, epoxy, BT resin, and other suitable materials being used to make the substrate, paragraph 33.
It would have been obvious to one having skill in the art at the effective filing date of the invention to use a common polymer material such as thermoset epoxy-based film and C-stage resin film to make a substrate in order to mount electronic component and form a complete circuit board.
Regarding claim 15, Fillion discloses the claimed invention as set forth in claim 10.
Fillion does not explicitly disclose the substrate is comprised of a thermoplastic polyurethane.
Fillion suggests the substrate is made of polymer film or other suitable materials (paragraph 33).
It would have been obvious to one having skill in the art at the effective filing date of the invention to use one of the polymers such as thermoplastic polyurethane which is relatively common due to lower price compared to polyimide which is also being recommended by Fillion as an option when cost of the production may be a factor in choosing the material.
Regarding claim 16, Fillion discloses the claimed invention as set forth in claim 10.
Fillion does not explicitly disclose the substrate is comprised of at least one of: a thermoset epoxy-based film and a C-stage resin film.
Fillion suggests polymer, epoxy, BT resin, and other suitable materials being used to make the substrate, paragraph 33.
It would have been obvious to one having skill in the art at the effective filing date of the invention to use a common polymer material such as thermoset epoxy-based film and C-stage resin film to make a substrate in order to mount electronic component and form a complete circuit board.
Claim(s) 9, 18, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fillion (US 20190304910), in view of Tsai (US 20200058606).
Regarding claim 9, Fillion discloses the claimed invention as set forth in claim 1.
Fillion does not explicitly disclose a release layer on at least one major surface of the substrate, the release layer configured to be removed to expose the adhesive property.
Tsai teaches a release layer, paragraph 31, being removed from the substrate 201 to expose the adhesive of the substrate (the adhesive of the substrate as discussed in claim 1).
It would have been obvious to one having skill in the art at the effective filing date of the invention to use a release layer to cover the adhesive surface of a substrate before use in order to protect the adhesive surface from being contaminated by particles in the environment.
Regarding claim 18, Fillion discloses the claimed invention as set forth in claim 10.
Fillion does not explicitly disclose a release layer on at least one major surface of the substrate, the release layer configured to be removed to expose the adhesive property.
Tsai teaches a release layer, paragraph 31, being removed from the substrate 201 to expose the adhesive of the substrate (the adhesive of the substrate as discussed in claim 1).
It would have been obvious to one having skill in the art at the effective filing date of the invention to use a release layer to cover the adhesive surface of a substrate before use in order to protect the adhesive surface from being contaminated by particles in the environment.
Regarding claim 19, Fillion discloses the claimed invention as set forth in claim 10.
Fillion does not explicitly disclose the second electronic component is a printed circuit board (PCB) and the adhesive property causes the substrate to adhere to the PCB.
Tsai suggests the substrate 100 is a PCB (paragraph 16). The substrate identical to the substrate 100 is a component attached to another substrate, Fig. 24.
It would have been obvious to one having skill in the art at the effective filing date of the invention to couple a PCB to a substrate in order to fit all the intended components into the electronic device.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Appeaning (US 20190330498) discloses a release layer on a substrate, Fig. 1.
Kapusta (US 20190043733) discloses a substrate having a component, a via, Fig. 4.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BINH B TRAN whose telephone number is (571)272-9289. The examiner can normally be reached M-F 8:00 AM - 6:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy J Dole can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BINH B TRAN/Primary Examiner, Art Unit 2847
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