Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4 and 6 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Du (US 20240321821).
Regarding claim 1. Du discloses A high-bandwidth memory (HBM) device (Fig 45, [0152]-[0168]), comprising:
a first die with an upper surface, a signal routing region, and a thermal region;
Du discloses a first die 420 having an upper surface upon which a plurality of memory dies are stacked (Fig. 45). The central portion of first die 420 includes conductive vias 431 configured for signal transmission, thereby corresponding to the claimed signal routing region. The lateral portions of first die 420 include heat-dissipation vias 421, thereby corresponding to the claimed thermal region.
a plurality of second dies carried by the upper surface of the first die, the plurality of second dies including an uppermost die;
Du discloses a plurality of stacked semiconductor memory dies 440 disposed on the upper surface of first die 420, the stack including an uppermost memory die located beneath the upper heat-dissipation structure (Fig. 45).
one or more active through substrate vias (TSVs) positioned within a footprint of the signal routing region and extending from a first metallization layer in the first die to a second metallization layer in the uppermost die;
Du discloses conductive vias 431 extending vertically through the stacked dies within the central signal transmission region (Fig. 45). The lower end of each conductive via 431 is electrically connected to conductive metallization formed in first die 420, corresponding to the claimed first metallization layer, while the upper end of each conductive via 431 is electrically connected to conductive metallization formed in the uppermost memory die, corresponding to the claimed second metallization layer. Accordingly, conductive vias 431 extend from a first metallization layer in the first die to a second metallization layer in the uppermost die, as claimed.
and a cooling network configured to transport heat away from the first die, the cooling network comprising:
Du discloses a heat-dissipation structure including heat-dissipation vias 421, conductive layers/pads 441, 442, 443, and upper heat-dissipation structures 450, collectively providing a thermal conduction path for transporting heat away from first die 420 through the stacked package (Figs. 41 and 45).
a thermally conductive layer carried by the upper surface of the first die over the thermal region;
Du discloses conductive layer 441 disposed on the upper surface of first die 420 within the heat-dissipation region (Fig. 41). Conductive layer 441 is a metal layer positioned over the thermal region containing heat-dissipation vias 421 and forms part of the thermal conduction path. Under the broadest reasonable interpretation, conductive layer 441 corresponds to the claimed thermally conductive layer because it is a conductive layer carried on the upper surface of the first die in the thermal region and functions to conduct heat within the cooling network.
and one or more cooling TSVs in contact with the thermally conductive layer and extending from the thermally conductive layer to an elevation at or above a top surface of the uppermost die.
Du discloses heat-dissipation vias 421 extending vertically through the stacked semiconductor dies (Fig. 45). As shown in Figs. 41 and 45, heat-dissipation vias 421 are in direct contact with conductive layer 441 on the upper surface of first die 420 and continue through corresponding conductive layers 442 and 443 formed between adjacent dies, thereby establishing a continuous thermal conduction path through the stacked memory device to an elevation at or above the uppermost memory die. Accordingly, heat-dissipation vias 421 correspond to the claimed cooling TSVs.
Therefore, Du discloses each and every limitation of claim 1. Accordingly, claim 1 is anticipated by Du.
Regarding claim 2. Du discloses The HBM device of claim 1 wherein the thermally conductive layer is a first thermally conductive layer, wherein the cooling network further comprises a second thermally conductive layer carried by the top surface of the uppermost die, and wherein the second thermally conductive layer is in contact with each of the one or more cooling TSVs (Du further discloses that the cooling network comprises a second thermally conductive layer disposed at the upper portion of the stacked memory device. As shown in Fig. 45, conductive layer 450 is carried by the uppermost semiconductor die and is electrically and thermally connected to the upper heat-dissipation structure 411. Heat transported upward through the heat-dissipation vias 421 is transferred into conductive layer 450, which in turn transfers the heat to heat-dissipation structure 411. Accordingly, conductive layer 450 corresponds to the claimed second thermally conductive layer because it is a conductive layer carried by the uppermost die and forms part of the cooling network for transporting heat away from the stacked memory device).
Regarding claim 4. Du discloses The HBM device of claim 1 wherein the cooling network further comprises a third die carried by the uppermost die, and wherein the elevation is at or above an uppermost surface of the third die (Du further discloses that the cooling network comprises a third die carried by the uppermost memory die. Specifically, Fig. 44 discloses an additional chip 410 disposed above the uppermost memory die, and paragraph [0166] identifies chip 410 as a chip. Accordingly, chip 410 corresponds to the claimed third die carried by the uppermost memory die.
Du further discloses that the cooling network extends through the stacked memory device to the chip. As shown in Fig. 45, heat-dissipation vias 421 are thermally connected through conductive layers 441, 442, and 443, and continue upward to conductive structure 433 located on the chip 410. Thus, the cooling TSVs extend to an elevation at or above the uppermost surface of the third die (chip 410), as required by the claim).
Regarding claim 6. Du discloses The HBM device of claim 1 wherein the first die includes a dielectric layer electrically insulating the thermal region of the upper surface, and wherein the thermally conductive layer is in contact with the dielectric layer (Du further discloses that the second thermally conductive layer is disposed on an upper surface of the third die. Specifically, Fig. 45 illustrates chip 410 corresponding to the claimed third die. Du further discloses insulating layer 443 disposed on the upper surface of chip 410. As explained in paragraph [0180], layer 443 is an insulating layer that carries conductive metallization forming part of the thermal conduction path. The conductive metallization disposed within insulating layer 443 corresponds to the claimed second thermally conductive layer.
Further, Fig. 45 illustrates that heat-dissipation TSVs 421 extend upward through the stacked semiconductor device and are in direct thermal contact with the conductive metallization carried by insulating layer 443, thereby providing a continuous thermal conduction path from conductive layer 441 through heat-dissipation TSVs 421 to the upper thermal structures. Accordingly, the second thermally conductive layer is in contact with the cooling TSVs, as required by the claim).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 7 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Du et al. (US 20240321821) in view of Kim et al. (US 20250062257).
Regarding claim 3. Du discloses the HBM device of claim 1 including a first die 420, a plurality of stacked memory dies 440, active TSVs 431, cooling TSVs 421, and a cooling network including conductive layer 441, as discussed above.
But Du does not explicitly disclose that the cooling TSVs extend to a first elevation, while the active TSVs extend to a second elevation beneath the first elevation, as recited.
However, Kim teaches the claimed relative elevation arrangement. Specifically, Fig. 1 discloses a thermally conductive layer 170, including conductive portion 171, disposed above the uppermost semiconductor die 110F. The top surface of thermally conductive layer 170 (particularly conductive portion 171) defines the claimed first elevation. Kim further discloses that the signal through vias 140 terminate at the top surface of the uppermost semiconductor die 110F, thereby defining a second elevation located beneath the first elevation. Thus, Kim teaches a structure in which the thermally conductive layer extends to a higher elevation than the termination of the signal through vias. Paragraph [0039] further explains that conductive portion 171 laterally transfers heat toward the thermal conduction structures.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Du's HBM device to incorporate the relative elevation arrangement taught by Kim because Kim teaches extending the thermally conductive layer above the termination of the signal through vias to improve heat dissipation in stacked semiconductor devices. Applying Kim's known thermal management structure to Du's HBM cooling network would have predictably enhanced heat removal from the interface die while preserving the signal transmission function of Du's active TSVs.
Accordingly, the combined teachings of Du and Kim teach or suggest the additional limitation of claim 3. Therefore, claim 3 would have been obvious to one of ordinary skill in the art at the time of the invention.
Regarding claim 7. Du discloses the HBM device of claim 1, including first die 420, stacked memory dies 440, thermally conductive layer 441, and cooling TSVs 421, as discussed above. But Du does not expressly disclose a dielectric layer formed over the thermally conductive layer that includes openings through which the cooling TSVs directly contact the thermally conductive layer.
However, Kim teaches this feature. Specifically, Fig. 3 discloses a third dielectric layer 336 formed over cooling layer 352. Paragraph [0034] explains that the third dielectric layer 336 is formed over the cooling layer 352 to protect the cooling layer and includes a plurality of openings 337 that allow the cooling TSVs 354 to make direct contact with the cooling layer 352. Thus, Kim expressly teaches a dielectric layer formed over at least a portion of the thermally conductive layer, wherein the dielectric layer includes openings corresponding to the cooling TSVs to permit the cooling TSVs to contact the thermally conductive layer through the dielectric layer.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Du's cooling network by providing the protective dielectric layer with openings taught by Kim because Kim teaches that the dielectric layer protects the thermally conductive layer while maintaining direct thermal contact between the cooling TSVs and the thermally conductive layer through the openings. Incorporating Kim's dielectric layer into Du's HBM cooling network would have predictably improved protection of the thermally conductive layer without degrading thermal conduction through the cooling TSVs. Accordingly, the combined teachings of Du and Kim teach or suggest the additional limitation of claim 7.
Regarding claim 17. Du discloses a stacked semiconductor device (Fig. 45; [0152]-[0168]) comprising: an interface die 420 having an active signal routing region including signal TSVs 431 and an active circuit region including heat-dissipation TSVs 421;
a plurality of memory dies 440 carried by the upper surface of the interface die;
signal TSVs 431 extending from conductive metallization in the interface die to conductive metallization in the uppermost memory die;
a conductive layer 441 disposed on the upper surface of the interface die within the thermal region; and
a plurality of heat-dissipation TSVs 421 thermally coupled to conductive layer 441 and extending through the stacked memory dies to an elevation at or above the uppermost memory die, thereby transporting heat away from the interface die.
But Du does not explicitly disclose that the cooling layer is configured to communicate heat laterally toward the contact points between the cooling layer and the cooling TSVs.
However, Kim discloses a conductive layer 171 disposed above the semiconductor body and thermally connected to heat-dissipation vias 140 and heat-dissipation pads 180 (Fig. 1). Kim explains that heat generated in the semiconductor body is transferred through the through via to the conductive layer 171, which laterally distributes the heat to the heat-dissipation pads before the heat is dissipated through the associated thermal structures. Kim further teaches that the conductive layer may be formed as a conductive pattern that overlaps the heat-dissipation pads and through vias to improve heat dissipation by increasing the lateral heat-transfer area. See, e.g., [0039], [0053]–[0059] and Figs. 1 and 2.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Du's cooling layer 441 to operate in the manner taught by Kim, such that the cooling layer laterally communicates heat toward the contact points with the cooling TSVs. Both Du and Kim are directed to thermal management in semiconductor devices employing thermal conduction structures. Kim teaches that laterally distributing heat through a conductive layer before transferring the heat into thermal vias improves heat dissipation efficiency by increasing the effective heat-transfer area and reducing localized heat concentration. Applying Kim's known lateral heat-spreading technique to Du's stacked HBM cooling network would have predictably improved heat removal from the interface die while preserving Du's existing vertical heat-conduction path through heat-dissipation TSVs. Such a modification represents the predictable use of a known thermal-management technique to improve the performance of a known stacked semiconductor package. Accordingly, the combined teachings of Du and Kim teach or suggest every limitation of claim 17, and claim 17 would have been obvious to one of ordinary skill in the art.
Regarding claim 18. Du and Kim collectively disclose the stacked semiconductor device of claim 17, as discussed above. Specifically, Du teaches the stacked memory device including cooling TSVs 421, while Kim teaches the cooling layer extending laterally toward contact points with the cooling TSVs.
Kim further discloses the additional limitation of claim 18. Specifically, Fig. 1 illustrates cooling layer 170, particularly conductive portion 171, extending laterally to contact points where the cooling layer directly contacts the upper ends of cooling TSVs 140. Paragraph [0039] explains that the cooling layer communicates heat laterally toward the contact points. Accordingly, the proximal region of each cooling TSV is in direct contact with the cooling layer at the contact point, as recited.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the direct-contact arrangement taught by Kim into Du's stacked semiconductor device because direct thermal contact between the cooling TSVs and the cooling layer improves heat transfer efficiency while maintaining the overall cooling network. Accordingly, the combined teachings of Du and Kim teach or suggest the additional limitation of claim 18.
Regarding claim 19. Du and Kim collectively disclose the stacked semiconductor device of claim 17, as discussed above. Du further discloses the additional limitation of claim 19. Specifically, Fig. 45 illustrates that the cooling TSVs 421 extend vertically through the stacked semiconductor device and pass through each memory die 440. Figures 6–8 provide the detailed interconnection structure between adjacent semiconductor dies. As shown in Fig. 7, each thermal via 111 and signal TSV 131 is coupled through lower soldering pad (or copper pad) 113 and upper soldering pad 135. Paragraph [0048] discloses that element 113 is a soldering pad or copper pad, while paragraph [0051] discloses that element 135 is a soldering pad. Accordingly, the conductive pads disposed on the upper surface of each memory die correspond to the claimed second cooling layer, and the cooling TSVs extend through and are thermally coupled to the conductive pads at each die interface. The same interconnection configuration is represented in the stacked memory device of Fig. 45, wherein the conductive pads interconnect the cooling TSVs between adjacent memory dies. Therefore, Du teaches a second cooling layer carried by the upper surface of the lowermost memory die, wherein the cooling TSVs extend through and are thermally coupled to the second cooling layer. Accordingly, the combined teachings of Du and Kim teach or suggest the additional limitation of claim 19. Therefore, claim 19 would have been obvious to one of ordinary skill in the art at the time the invention was made.
Regarding claim 20. Du and Kim collectively disclose the stacked semiconductor device of claim 17, as discussed above. Du further discloses the additional limitation of claim 20. Specifically, Fig. 45 illustrates conductive layer 450 disposed at the distal ends of heat-dissipation TSVs 421. Conductive layer 450 is thermally coupled to the distal regions of the cooling TSVs and functions as a second cooling layer for transferring heat from the cooling TSVs to the upper heat-spreading structure 411. Accordingly, Du teaches a second cooling layer thermally coupled to the distal region of each of the plurality of cooling TSVs, as recited. Accordingly, the combined teachings of Du and Kim teach or suggest the additional limitation of claim 20.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Du et al. (US 20240321821) in view of Lin et al. (US 20210159147).
Regarding claim 5. Du discloses the HBM device of claim 4, including first thermally conductive layer 441, the chip 410 corresponding to the claimed third die, and cooling TSVs 421 thermally coupled through the stacked device.
Du does not expressly disclose that the third die is at least partially wrapped in a second thermally conductive layer.
Lin teaches this feature. Lin discloses thermal conductive layer/pattern 160/108 disposed around semiconductor die 110 to provide thermal coupling and heat dissipation. In particular, Lin’s top views in Figs. 3–8 show thermal conductive structures surrounding or partially surrounding the semiconductor die, and Lin explains that thermal conductive pattern 108 surrounds the semiconductor die and is thermally coupled through thermal conductive layer 160. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Du’s chip 410 by providing Lin’s partially surrounding/wrapping thermally conductive layer arrangement because Lin teaches that such thermally conductive structures improve heat dissipation by thermally coupling the die to surrounding thermal conductive structures. The modification would predictably increase heat transfer area around Du’s chip and improve heat removal from Du’s cooling TSV network.
Claims 8-12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable Tong et al. (US 20240128146) in view of Du et al. (US 20240321821).
Regarding claim 8. Tong discloses A system-in-package (SiP) device (Fig 18, [0112]), comprising:
an interposer substrate 303;
a processing unit 311 [0112] carried by the interposer substrate; and
a high-bandwidth memory (HBM) device 302 [0112] carried by the interposer substrate, wherein the HBM device is coupled to the processing unit by an interposer bus (Fig 18), and wherein the HBM device comprises:
an interface die 3021 [0112] carried by the interposer substrate;
a plurality of memory dies 3022 [0112] carried by the interface die;
a plurality of first through substrate vias (TSVs) communicably coupling each of the plurality of memory dies and the interface die (Fig 18).
But Tong does not disclose a cooling network configured to transport heat away from the interface die, wherein the cooling network comprises: a conductive layer thermally coupled to and carried by an upper surface of the interface die; and a plurality of second TSVs thermally coupled to the conductive layer and extending from the conductive layer to an elevation at or above a top surface of an uppermost memory die.
However, Du teaches these features. Specifically, Du discloses a cooling network for a stacked HBM device including a conductive layer 441 disposed on the upper surface of interface die 420 within the thermal region (Fig. 41). As shown in Figs. 41 and 45, conductive layer 441 is thermally coupled to heat-dissipation vias 421, which extend vertically through the stacked memory dies. The heat-dissipation vias are interconnected through conductive metallization layers (e.g., 441, 442, and 443) to form a continuous thermal conduction path extending to an elevation at or above the uppermost memory die, thereby transporting heat away from the interface die. Under the broadest reasonable interpretation, conductive layer 441 corresponds to the claimed conductive layer and heat-dissipation vias 421 correspond to the claimed plurality of second TSVs.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Tong's HBM device by incorporating the cooling network taught by Du. Tong and Du are directed to the same field of stacked semiconductor packaging and HBM technology, and both address thermal management in vertically stacked semiconductor devices. Incorporating Du's conductive layer and thermally coupled heat-dissipation TSVs into Tong's HBM device would have predictably improved the dissipation of heat generated within the interface die by providing an additional thermal conduction path from the interface die through the memory stack. Such a modification merely applies a known thermal management technique to Tong's known HBM package to obtain the predictable result of improved heat removal, reduced thermal accumulation, and enhanced device reliability.
Accordingly, the combined teachings of Tong and Du disclose or suggest every limitation of claim 8. Therefore, claim 8 would have been obvious to one of ordinary skill in the art at the time of the invention.
Regarding claim 9. Tong in view of Du discloses The SiP device of claim 8, Du further discloses that the conductive layer is a first conductive layer, and that the cooling network further comprises a second conductive layer carried by the top surface of the uppermost memory die. Specifically, as shown in Fig. 45, conductive layer 441 is disposed on the upper surface of interface die 420, corresponding to the claimed first conductive layer. Du further discloses conductive layer 450 carried by the top surface of the uppermost memory die, wherein conductive layer 450 is in direct thermal contact with heat-dissipation TSVs 421. Accordingly, conductive layer 450 corresponds to the claimed second conductive layer thermally coupled to the plurality of second TSVs).
Regarding claim 10. Tong in view of Du discloses The SiP device of claim 8, Du further discloses a thermal dissipation die carried by the uppermost memory die. Specifically, Fig. 44 illustrates chip 410 disposed above the uppermost memory die, and paragraph [0166] identifies chip 410 as a chip. Under the broadest reasonable interpretation, chip 410 corresponds to the claimed thermal dissipation die because it is a die incorporated into the thermal conduction path for dissipating heat from the stacked memory device. Further, as shown in Fig. 45, heat-dissipation TSVs 421 extend vertically through the stacked memory device and continue through chip 410. Accordingly, Du teaches that the plurality of second TSVs extend through the thermal dissipation die, as recited).
Regarding claim 11. Tong in view of Du discloses The SiP device of claim 8, Tong further discloses the additional limitations of claim 11. Specifically, Fig. 18 illustrates that the top surface of processing unit 311 is substantially coplanar with the top surface of HBM device 302, such that both top surfaces directly contact heat spreader 3503A. Paragraph [0114] identifies element 3503A as a heat spreader. Accordingly, heat spreader 3503A corresponds to the claimed cooling media carried by the top surface of the processing unit and the top surface of the HBM device. Further, because heat spreader 3503A is in direct thermal contact with the top surface of HBM device 302, which includes the cooling network supplied by Du, heat spreader 3503A is thermally coupled to the cooling network in the HBM device.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the heat spreader arrangement taught by Tong in the combined SiP device because Tong teaches that a common heat spreader contacting both the processing unit and the HBM device efficiently removes heat from both components. Applying Tong's heat spreader to the HBM cooling network provided by Du would have predictably improved overall thermal dissipation and package reliability.
Regarding claim 12. Tong in view of Du discloses The SiP device of claim 8, Du further discloses the additional limitation of claim 12. Specifically, paragraph [0009] discloses that die 420 is a buffer chip, and Figs. 41 and 45 illustrate conductive layer 441 disposed on the upper surface of buffer chip 420 within the thermal region. As further shown in Fig. 45 and described in paragraph [0168], the thermal region includes heat-dissipation vias 421, which are configured to dissipate heat generated by the buffer chip. Accordingly, conductive layer 441 is positioned directly over the thermal region of the buffer chip and is therefore vertically aligned with one or more active circuits in the interface die, as recited.
Regarding claim 14. Tong in view of Du discloses The SiP device of claim 8. Du further discloses the additional limitations of claim 14. Specifically, paragraph [0180] and Fig. 43 disclose that each conductive via 431 is electrically interconnected between the buffer chip 420 and the adjacent second memory chip 440 through a third metal soldering pad 441 and a first conductive bump 442. Paragraph [0180] further teaches that each first conductive bump 442 respectively corresponds to the conductive vias 431 and second heat-dissipation vias 421, and that the first conductive bumps 442 are copper-tin bumps. Accordingly, each conductive via comprises a first TSV segment formed in the interface die (buffer chip 420) and a second TSV segment formed in the lowermost memory die 440, wherein the first TSV segment is electrically coupled to the second TSV segment via the copper-tin bump 442, corresponding to the claimed solder structure.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Du's segmented TSV interconnection into Tong's HBM device because Du teaches that copper-tin bump interconnections provide reliable electrical connections between vertically stacked semiconductor dies while accommodating high-density memory packaging. Accordingly, the combined teachings of Tong and Du teach or suggest the additional limitation of claim 14. Therefore, claim 14 would have been obvious to one of ordinary skill in the art at the time the invention was made.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable Tong et al. (US 20240128146) in view of Du et al. (US 20240321821), and further in view of Choi et al. (US 20210343616).
Regarding claim 13. Tong in view of Du discloses The SiP device of claim 8, Specifically, Tong teaches a system-in-package (SiP) device including a processing unit and a high-bandwidth memory (HBM) device, while Du teaches the HBM device including a plurality of first TSVs (active TSVs 431) and a plurality of second TSVs (cooling TSVs 421).
But Tong in view of Du does not expressly disclose that the plurality of first TSVs have a first pitch and the plurality of second TSVs have a second pitch smaller than the first pitch, as recited.
However, Choi teaches the claimed pitch relationship. Specifically, Fig. 4D illustrates a semiconductor chip including a signal region (SR) and a thermal region (TR) divided into a first thermal region (TR1) and a second thermal region (TR2). Paragraph [0069] discloses that the semiconductor chip includes signal vias PVA-S and thermal vias PVA-T, wherein the thermal vias PVA-T correspond to the connecting vias 245. Paragraph [0065] further explains that TR1 is adjacent the signal region SR, whereas TR2 is located closer to the edge of the semiconductor chip. Paragraph [0107] expressly teaches that the pitch PT-X associated with the thermal vias PVA-T in TR1 is smaller than the pitch PTL-X associated with the thermal vias PVA-T in TR2, and that PTL-X may be two, three, or more times greater than PT-X. Accordingly, Choi expressly teaches a plurality of thermal vias having different pitches, with the thermal vias in TR1 arranged at a smaller pitch than the thermal vias in TR2. Under the broadest reasonable interpretation, the thermal vias PVA-T correspond to the claimed plurality of second TSVs having a second pitch that is smaller than the first pitch of another plurality of TSVs.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the HBM device of Tong and Du to incorporate the thermal-via pitch arrangement taught by Choi because Choi teaches that varying the density of thermal vias in different thermal regions enhances heat dissipation while accommodating routing and package layout constraints. Applying Choi's known thermal-via pitch arrangement to the cooling TSVs of Du would have predictably improve thermal removal from the HBM device while maintaining the signal transmission functionality of the active TSVs. Accordingly, the combined teachings of Tong, Du, and Choi teach or suggest the additional limitation of claim 13. Therefore, claim 13 would have been obvious to one of ordinary skill in the art at the time the invention was made.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable Tong et al. (US 20240128146) in view of Du et al. (US 20240321821), and further in view of Kim et al. (US 20250062257).
Regarding claim 15. Tong in view of Du discloses The SiP device of claim 14. But Tong in view of Du does not expressly disclose wherein a top surface of the first TSV segment is at a different elevation than a top surface of the conductive layer.
However, Kim teaches the claimed relative elevation. Specifically, Fig. 1 discloses that conductive layer 170 extends above the uppermost semiconductor die, while the signal through vias 140 terminate at the upper surface of semiconductor die 110F. Thus, the top surface of the signal TSVs is positioned at a different elevation than the top surface of conductive layer 170.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the SiP device of Tong and Du to incorporate the relative elevation arrangement taught by Kim because Kim teaches that positioning the conductive layer above the TSV termination improves heat spreading while maintaining signal interconnection. Accordingly, the combined teachings of Tong, Du, and Kim teach or suggest the additional limitation of claim 15.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable Tong et al. (US 20240128146) in view of Du et al. (US 20240321821), and further in view of Choi et al. (US 20210343616).
Regarding claim 16. Tong in view of Du discloses The SiP device of claim 8. Specifically, Tong teaches the system-in-package (SiP) architecture including the processing unit and the high-bandwidth memory (HBM) device, while Du teaches the conductive layer 441 disposed on the upper surface of interface die 420 as part of the cooling network.
But Tong in view of Du does not expressly disclose wherein the conductive layer is formed in a mesh pattern over the upper surface of the interface die.
Choi teaches this feature. Specifically, Fig. 4C illustrates a signal region (SR) and a thermal region (TR). Paragraph [0073] discloses that the front surface openings PVO are filled with signal vias PVA-S in the signal region SR and thermal vias PVA-T in the thermal region TR. Figure 4C further illustrates that the thermal vias PVA-T are interconnected by conductive metal wiring MLx, forming an interconnected mesh (grid) pattern across the thermal region. Thus, Choi teaches a conductive layer formed as a mesh pattern over the semiconductor substrate for thermally interconnecting a plurality of thermal vias, corresponding to the claimed conductive layer formed in a mesh pattern over the upper surface of the interface die.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the conductive layer 441 of Du to adopt the mesh-pattern configuration taught by Choi because Choi teaches that an interconnected conductive mesh distributes heat laterally among multiple thermal vias, thereby improving heat spreading and overall thermal dissipation. Applying Choi's known mesh-pattern conductive layer to the HBM cooling network of Tong and Du would have predictably enhanced thermal performance while maintaining the vertical heat-transfer function of the cooling TSVs. Accordingly, the combined teachings of Tong, Du, and Choi teach or suggest the additional limitation of claim 16. Therefore, claim 16 would have been obvious to one of ordinary skill in the art at the time the invention was made.
Conclusion
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/Changhyun Yi/Primary Examiner, Art Unit 2812
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