DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending and examined.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4, 9-12, 14, 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by PGPub. 2024/0079056 to Dong et al. (hereafter Dong).
Regarding independent claim 1, Dong teaches a method for performing an erase operation in a memory device, comprising:
before applying an erase pulse to a source line coupled to a memory cell array of the memory device (FIG. 7A: before applying erase pulse to source line in second phase), separately performing pre-programming operations on word lines and select gate lines of the memory cell array, wherein the select gate lines comprise a first select gate line (FIG. 7A: pre-programming word line and select line DSG in first phase; also see FIG. 7B and par. [0119]), and wherein separately performing the pre-programming operations on the word lines and the select gate lines comprises:
performing a first pre-programing operation on the word lines in a first time period (see annotated FIG. 7B below and par. [0119]); and
performing a second pre-programing operation on the first select gate line in a second time period different from the first time period (see annotated FIG. 7B below and par. [0119]); and
applying the erase pulse to the source line (FIG. 7A: applying V4 to source line).
Annotated FIG. 7B
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Regarding dependent claim 2, Dong teaches wherein the method comprises: when applying the erase pulse to the source line, maintaining a voltage of the select gate lines at an initial voltage in an initial phase of the erase pulse, wherein a voltage of the erase pulse increases over time in the initial phase; and in response to determining that the erase pulse reaches a threshold, floating the select gate lines (see par. [0096]).
Regarding dependent claim 4, Dong teaches wherein performing the first pre-programing operation on the word lines in the first time period comprises: applying a first voltage to the word lines in the first time period (FIG. 7B: applying Vpe_3 to word line at t1_1); and applying a second voltage to the first select gate line in the first time period (FIG. 7B: applying Vpe_1 to word line at t1_1), wherein the first voltage is higher than the second voltage (FIG. 7B: Vpe_3>Vpe_1, see par. [0108]).
Regarding dependent claim 9, Dong teaches wherein: the select gate lines further comprise a second select gate line (FIG. 8B: select lines SSG line_1); and separately performing the pre-programming operations on the word lines and the select gate lines further comprises: performing a third pre-programing operation on the second select gate line in a third time period, wherein the third time period is different from the first time period and the second time period (FIG. 8C: pre-program periods/durations for SSG line_0 and SSG line_1 are different).
Regarding dependent claim 10, Dong teaches wherein the first select gate line and the second select gate line are bottom select gate (BSG) lines (see FIG. 8A).
Regarding independent claim 11, Dong teaches a memory device, comprising:
a memory cell array (FIG. 5: memory cell array 502); and
a peripheral circuit coupled to the memory cell array (other elements of FIG. 5 except memory cell array 502), wherein the peripheral circuit is configured to:
before applying an erase pulse to a source line coupled to the memory cell array of the memory device (FIG. 7A: before applying erase pulse to source line in second phase), separately perform pre-programming operations on word lines and select gate lines of the memory cell array, wherein the select gate lines comprise a first select gate line (FIG. 7A: pre-programming word line and select line DSG in first phase; also see FIG. 7B and par. [0119]), and wherein separately performing the pre-programming operations on the word lines and the select gate lines comprises:
performing a first pre-programing operation on the word lines in a first time period (see annotated FIG. 7B above and par. [0119]); and
performing a second pre-programing operation on the first select gate line in a second time period different from the first time period (see annotated FIG. 7B above and par. [0119]); and
apply the erase pulse to the source line (FIG. 7A: applying V4 to source line).
Regarding dependent claim 12, Dong teaches wherein the peripheral circuit is configured to: when applying the erase pulse to the source line (FIG. 7A: second phase), maintain a voltage of the select gate lines at an initial voltage in an initial phase of the erase pulse (FIG. 7A: maintaining Vh on SSG line during t2-t3), wherein a voltage of the erase pulse progressively increases over time in the initial phase (FIG. 7A: voltage on source line is increasing during t2-t3); and in response to determining that the erase pulse reaches a predetermined threshold, start to increase the voltage of the select gate lines (FIG. 7A: floating SSG line to coupling voltage V5 after t3).
Regarding dependent claim 14, see rejection applied to claim 4 above.
Regarding dependent claim 19, see rejection applied to claim 9 above.
Regarding independent claim 20, Dong teaches a system, comprising a memory device and a controller coupled to the memory device (see FIG. 2A), wherein the memory device (see FIG. 5) comprises:
a memory cell array (FIG. 5: memory cell array 502); and
a peripheral circuit coupled to the memory cell array (other elements of FIG. 5 except memory cell array 502), wherein the peripheral circuit is configured to:
before applying an erase pulse to a source line coupled to the memory cell array of the memory device (FIG. 7A: before applying erase pulse to source line in second phase), separately perform pre-programming operations on word lines and select gate lines of the memory cell array, wherein the select gate lines comprise a first select gate line (FIG. 7A: pre-programming word line and select line DSG in first phase; also see FIG. 7B and par. [0119]), and wherein separately performing the pre-programming operations on the word lines and the select gate lines comprises:
performing a first pre-programing operation on the word lines in a first time period (see annotated FIG. 7B above and par. [0119]);; and
performing a second pre-programing operation on the first select gate line in a second time period different from the first time period (see annotated FIG. 7B above and par. [0119]); and
apply the erase pulse to the source line (FIG. 7A: applying V4 to source line).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 5, 7-8, 13, 15, 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Dong.
Regarding dependent claim 3, Dong does not explicitly teach wherein a starting time point of the second time period is prior to a starting time point of the first time period. However, Dong suggest the first time period and the second time period may or may not overlap (see par. [0119]). This gives possibility that a starting time point of the second time period may be prior to a starting time point of the first time period as recited in claim.
Regarding dependent claim 5, Dong does not explicitly teach wherein the first voltage is a program voltage, and the second voltage is a pass voltage. However, Dong suggest the first time period and the second time period may or may not overlap (see par. [0119]). This gives possibility that when the voltage pulse applied to word line before voltage pulse applied to select line, and they are somewhat overlapped, the word line may reach the Vpe_3 while select line is still at Vpass.
Regarding dependent claim 7, Dong does not explicitly teaches wherein performing the second pre-programing operation on the first select gate line in the second time period comprises: applying a third voltage to the first select gate line in the second time period; and applying a fourth voltage to the word lines in the second time period, wherein the third voltage is higher than the fourth voltage. However, Dong suggest the first time period and the second time period may or may not overlap (see par. [0119]). This gives possibility that when the voltage pulse applied to word line after voltage pulse applied to select line, and they are somewhat overlapped, the select line may reach the Vpe_1 while word line is still at Vpass.
Regarding dependent claim 8, Dong teaches wherein the third voltage is higher than the first voltage (FIG. 7B: Vpe_1 > Vpass).
Regarding dependent claim 13, see rejection applied to claim 3 above.
Regarding dependent claim 15, see rejection applied to claim 5 above.
Regarding dependent claims 17-18, see rejection applied to claims 7-8 above.
Allowable Subject Matter
Claims 6, 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to dependent claim 6: wherein a voltage level of the first voltage is in a range of 11-25 volts, and a voltage level of the second voltage is in a range of 3-11 volts.
With respect to dependent claim 16: wherein a voltage level of the first voltage is in a range of 11-25 volts, and a voltage level of the second voltage is in a range of 3-11 volts.
Conclusion
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January 24, 2026
/VANTHU T NGUYEN/Primary Examiner, Art Unit 2824