DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to 04/24/2026 Amendment.
Claims 1-3, 5-13, 15-22 are pending and examined. Claims 4, 14 have been cancelled. Claims 21-22 are newly added.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-13, 15-22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by PGPub. 2024/0079056 to Dong et al. (hereafter Dong).
Regarding independent claim 1, Dong teaches a method for performing an erase operation in a memory device, comprising:
before applying an erase pulse to a source line coupled to a memory cell array of the memory device (FIG. 7A: before applying erase pulse to source line in second phase), separately performing pre-programming operations on word lines and select gate lines of the memory cell array, wherein the select gate lines comprise a first select gate line (FIG. 7A: pre-programming word line and select line DSG in first phase; also see FIG. 7B and par. [0119]), and wherein separately performing the pre-programming operations on the word lines and the select gate lines comprises:
performing a first pre-programing operation on the word lines in a first time period, wherein performing the first pre-programing operation comprises applying a first voltage to the word lines in the first time period, and applying a second voltage to the first select gate line in the first time period, wherein a voltage level of the first voltage is greater than a voltage level of the second voltage (see Annotated FIG. 7B based on paragraph [0119] above. When V3=Vpe_3 is applied to word line in first time period for pre-programming operation, Vpass is inherently applied to select gate line in first time period to allow charge flowing through. It is clear that Vpe_3 > Vpass. First time period for pre-programming operation of word line maybe before or after second time period for pre-programming operation of select gate line); and
performing a second pre-programing operation on the first select gate line in a second time period different from the first time period (see Annotated FIG. 7B based on paragraph [0119] below, wherein V1=Vpe_1 is applied to select gate line in second time period different from first time period); and
applying the erase pulse to the source line (FIG. 7A: applying V4 to source line).
Annotated FIG. 7B based on paragraph [0119]
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Regarding dependent claim 2, Dong teaches wherein the method comprises: when applying the erase pulse to the source line, maintaining a voltage of the select gate lines at an initial voltage in an initial phase of the erase pulse, wherein a voltage of the erase pulse increases over time in the initial phase; and in response to determining that the erase pulse reaches a threshold, floating the select gate lines (see par. [0096]).
Regarding dependent claim 3, Dong implicitly teaches wherein a starting time point of the second time period is prior to a starting time point of the first time period (when select gate line is pre-programmed before word line).
Regarding dependent claim 5, Dong teaches wherein the first voltage is a program voltage (i.e. Vpre_3), and the second voltage is implicitly a pass voltage (because when selected word line is programmed, unselected word lines and select gate lines are applied with pass voltage to let charges flowing through, see [0094]).
Regarding dependent claim 6, Dong implicitly teaches wherein a voltage level of the first voltage is in a range of 11-25 volts (since V3>V1, with V1 for pre-programming select gate line ranges from 11V-15V, it is obvious that V3 for pre-programming word line is greater than 15V, see paragraph [0104]), and a voltage level of the second voltage is in a range of 3-11 volts (second voltage is a pass voltage Vpass. With V1 for pre-programming select gate line ranges from 11V-15V, and Vpass is seen higher than maximum read voltage but less than any program voltage, Vpass is seen in less than 11 V, see paragraph [0104]).
Regarding dependent claim 7, Dong implicitly teaches wherein performing the second pre-programing operation on the first select gate line in the second time period comprises: applying a third voltage to the first select gate line in the second time period; and applying a fourth voltage to the word lines in the second time period, wherein the third voltage is higher than the fourth voltage (see Annotated FIG. 7B based on paragraph [0119] above. When V1=Vpe_1 is applied to select gate line in second time period for pre-programming operation, Vpass is inherently applied to word line in second time period to allow charge flowing through. It is clear that Vpe_1 > Vpass).
Regarding dependent claim 8, Dong teaches wherein the third voltage is higher than the first voltage (because Vpass is seen higher than maximum read voltage but less than any program voltage such as Vpe_1, see paragraph [0104]).
Regarding dependent claim 9, Dong teaches wherein: the select gate lines further comprise a second select gate line (FIG. 8B: select lines SSG line_1); and separately performing the pre-programming operations on the word lines and the select gate lines further comprises: performing a third pre-programing operation on the second select gate line in a third time period, wherein the third time period is different from the first time period and the second time period (FIG. 8C: pre-program periods/durations for SSG line_0 and SSG line_1 are different).
Regarding dependent claim 10, Dong teaches wherein the first select gate line and the second select gate line are bottom select gate (BSG) lines (see FIG. 8A).
Regarding independent claim 11, Dong teaches a memory device, comprising:
a memory cell array (FIG. 5: memory cell array 502); and
a peripheral circuit coupled to the memory cell array (other elements of FIG. 5 except memory cell array 502), wherein the peripheral circuit is configured to:
before applying an erase pulse to a source line coupled to the memory cell array of the memory device (FIG. 7A: before applying erase pulse to source line in second phase), separately perform pre-programming operations on word lines and select gate lines of the memory cell array, wherein the select gate lines comprise a first select gate line (FIG. 7A: pre-programming word line and select line DSG in first phase; also see FIG. 7B and par. [0119]), and wherein separately performing the pre-programming operations on the word lines and the select gate lines comprises:
performing the first pre-programing operation comprises applying a first voltage to the word lines in the first time period, and applying a second voltage to the first select gate line in the first time period, wherein a voltage level of the first voltage is greater than a voltage level of the second voltage (see Annotated FIG. 7B based on paragraph [0119] above. When V3=Vpe_3 is applied to word line in first time period for pre-programming operation, Vpass is inherently applied to select gate line in first time period to allow charge flowing through. It is clear that Vpe_3 > Vpass. First time period for pre-programming operation of word line maybe before or after second time period for pre-programming operation of select gate line); and
performing a second pre-programing operation on the first select gate line in a second time period different from the first time period (see Annotated FIG. 7B based on paragraph [0119] above, wherein V1=Vpe_1 is applied to select gate line in second time period different from first time period); and
apply the erase pulse to the source line (FIG. 7A: applying V4 to source line).
Regarding dependent claim 12, Dong teaches wherein the peripheral circuit is configured to: when applying the erase pulse to the source line (FIG. 7A: second phase), maintain a voltage of the select gate lines at an initial voltage in an initial phase of the erase pulse (FIG. 7A: maintaining Vh on SSG line during t2-t3), wherein a voltage of the erase pulse progressively increases over time in the initial phase (FIG. 7A: voltage on source line is increasing during t2-t3); and in response to determining that the erase pulse reaches a predetermined threshold, start to increase the voltage of the select gate lines (FIG. 7A: floating SSG line to coupling voltage V5 after t3).
Regarding dependent claims 13, 15-19, see rejection applied to claims 3, 5-9 above.
Regarding independent claim 20, Dong teaches a system, comprising a memory device and a controller coupled to the memory device (see FIG. 2A), wherein the memory device (see FIG. 5) comprises:
a memory cell array (FIG. 5: memory cell array 502); and
a peripheral circuit coupled to the memory cell array (other elements of FIG. 5 except memory cell array 502), wherein the peripheral circuit is configured to:
before applying an erase pulse to a source line coupled to the memory cell array of the memory device (FIG. 7A: before applying erase pulse to source line in second phase), separately perform pre-programming operations on word lines and select gate lines of the memory cell array, wherein the select gate lines comprise a first select gate line (FIG. 7A: pre-programming word line and select line DSG in first phase; also see FIG. 7B and par. [0119]), and wherein separately performing the pre-programming operations on the word lines and the select gate lines comprises:
performing a first pre-programing operation on the word lines in a first time period, wherein performing the first pre-programing operation comprises applying a first voltage to the word lines in the first time period, and applying a second voltage to the first select gate line in the first time period, wherein a voltage level of the first voltage is greater than a voltage level of the second voltage (see Annotated FIG. 7B based on paragraph [0119] above. When V3=Vpe_3 is applied to word line in first time period for pre-programming operation, Vpass is inherently applied to select gate line in first time period to allow charge flowing through. It is clear that Vpe_3 > Vpass. First time period for pre-programming operation of word line maybe before or after second time period for pre-programming operation of select gate line); and
performing a second pre-programing operation on the first select gate line in a second time period different from the first time period (see Annotated FIG. 7B based on paragraph [0119] above, wherein V1=Vpe_1 is applied to select gate line in second time period different from first time period); and
apply the erase pulse to the source line (FIG. 7A: applying V4 to source line).
Regarding dependent claim 21, Dong teaches wherein the peripheral circuit is configured to: when applying the erase pulse to the source line (FIG. 7A: during second phase), maintain a voltage of the select gate lines at an initial voltage in an initial phase of the erase pulse (FIG. 7A: maintain voltage of select gate line SSG/DSG at Vh from t2-t3), wherein a voltage of the erase pulse increases over time in the initial phase (FIG. 7A: increasing voltage of source line from V2 to V4 during t2-t3); and in response to determining that the erase pulse reaches a threshold, float the select gate lines (see paragraph [0096]).
Regarding dependent claim 22, Dong teaches wherein a starting time point of the second time period is prior to a starting time point of the first time period (see Annotated FIG. 7B based on paragraph [0119] above).
Response to Arguments
Applicant's arguments filed 04/24/2025 have been fully considered but they are not persuasive.
Applicant argues:
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Examiner respectfully disagrees with Applicant’s argument. The recited features, as amended, suggest the first pre-programming operation on word line and second pre-programming operation on select gate line are performed at different timings. To which, Dong suggests in paragraph [0119]:
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Examiner has annotated FIG. 7B of Dong based on paragraph [0119]. Applicant is kindly reference to annotated FIG. 7B above for details.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VANTHU NGUYEN whose telephone number is (571)272-1881. The examiner can normally be reached M-F: 7:00AM - 3:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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May 25, 2026
/VANTHU T NGUYEN/Primary Examiner, Art Unit 2824
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