Prosecution Insights
Last updated: October 02, 2026
Application No. 18/777,935

DISPLAY SUBSTRATE AND DISPLAY DEVICE

Non-Final OA §103
Filed
Jul 19, 2024
Priority
Apr 09, 2020 — nonprovisional of PCTCN2020084024 +1 more
Examiner
NADAV, ORI
Art Unit
Tech Center
Assignee
BOE Technology Group Co., Ltd.
OA Round
1 (Non-Final)
60%
Grant Probability
Moderate
1-2
OA Rounds
1y 7m
Est. Remaining
81%
With Interview

Examiner Intelligence

Grants 60% of resolved cases
60%
Career Allowance Rate
426 granted / 710 resolved
At TC average
Strong +21% interview lift
Without
With
+21.2%
Interview Lift
resolved cases with interview
Typical timeline
3y 9m
Avg Prosecution
52 currently pending
Career history
778
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
55.5%
+15.5% vs TC avg
§102
9.8%
-30.2% vs TC avg
§112
30.9%
-9.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 710 resolved cases

Office Action

§103
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA DETAILED ACTION Election/Restrictions Applicant’s election without traverse of the embodiment of figure 7 in the reply filed on 08/27/2026 is acknowledged. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-13 are rejected under 35 U.S.C. 103 as being unpatentable over Heo et al. (KR10130068920, provided as IDS on 07/08/2021) in view of Yan et al. (2016/0372525).Regarding claim 1, Heo et al. teaches in figure 3 and related text a display substrate, comprising: a base substrate 110 comprising a display area which comprises a plurality of pixel unit areas; a first electrode layer 147 provided on a side of the base substrate and comprising three sub-electrodes (arbitrarily defined as being part of the first electrode layer 147), wherein an orthographic projection of the first electrode layer on the base substrate is located in the display area, and three sub-electrodes are provided in each of the pixel unit areas; a first light-emitting layer 230 provided on a side of the first electrode layer 147 away from the base substrate 110, and an orthographic projection of the first light-emitting layer 230 on the base substrate covering the display area; a first common connection layer 221, 222 provided on a side of the first light-emitting layer 230 away from the first electrode layer 147, used to transport holes, and comprising a first sub-common connection layer 221, 222, corresponding to the pixel unit area, wherein an orthographic projection of the first sub-common connection layer on the base substrate is at least partially located on the pixel unit area and covers at least a part of orthographic projections of the first sub-electrode 147 and the second sub-electrode 147 on the base substrate; a second light-emitting layer provided on a side of the first common connection layer 221, 222 away from the first light-emitting layer 230, comprising a second sub-light-emitting layer (arbitrarily defined as being part of the second light-emitting layer 231) corresponding to the pixel unit area, wherein an orthographic projection of the second sub- light-emitting layer on the base substrate is at least partially located within a range of the orthographic projection of the first sub-electrode on the base substrate; a connection layer (part of 221, 222) provided on the side of the first common connection layer away from the first light-emitting layer 231, used to transport the holes, comprising a sub-connection layer corresponding to the pixel unit area, wherein an orthographic projection of the sub-connection layer on the base substrate is at least partially located within a range of the orthographic projection of the second sub-electrode 147 on the base substrate; a third light-emitting layer 232 provided on a side of the connection layer away from the first light-emitting layer, comprising a third sub-light-emitting layer (arbitrarily defined as being part of the third light-emitting layer 231) corresponding to the sub-connection layer, wherein an orthographic projection of the third sub-light-emitting layer on the base substrate is at least partially located within a range of the orthographic projection of the second sub-electrode on the base substrate; and a second electrode layer (Cathode) provided on a side, away from the first electrode layer 147, of the second light-emitting layer and the third light-emitting layer (arbitrarily defined as being part of the third light-emitting layer 231), an orthographic projection of the second electrode layer on the base substrate covering orthographic projections of the first light-emitting layer, the second light-emitting layer, and the third light-emitting layer on the base substrate. Heo et al. do not explicitly state using a first electrode layer comprising a plurality of sub-electrodes, and second/third light-emitting layers comprising a plurality of second/third sub-light-emitting layers. Yan et al. teach in figure 3 and related text using a first electrode layer comprising a plurality of sub-electrodes 2, and second/third light-emitting layers comprising a plurality of second/third sub-light-emitting layers 401, 402, 403, 404. Yan et al. and Heo et al. are analogous art because they are directed to display devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Heo et al. because they are from the same field of endeavor.It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the first semiconductor layer of the first transistor of polycrystalline silicon and the second semiconductor layer of the second transistor of an oxide semiconductor, as taught by Yan et al., in Heo et al.’s device, in order to improve the light illumination of the device. Regarding claim 2, Heo et al. teach in figure 3 and related text that the orthographic projections of the second light-emitting layer 231 and the third light-emitting layer 232 on the base substrate do not overlap. Regarding claim 3, Heo et al. teach in figure 3 and related text a second common connection layer (the other one of 221 and 222) provided on a side of the first light-emitting layer 230 away from the first electrode layer, used to transport the holes, comprising a second sub-common connection layers (arbitrarily defined as being part of the second common connection layer) corresponding to the first sub-common connection layer; wherein the first common connection layer is located at a side of the second common connection layer away from the first light-emitting layer, and an orthographic projection of the second sub- common connection layer on the base substrate is at least partially located on the pixel unit area, and covers at least a part of the orthographic projections of the first sub-electrode and the second sub-electrode on the base substrate. Regarding claim 4, Heo et al. teach in figures 2-3 and related text a pixel defining layer 150 (see figure 2) provided on a side of the first electrode layer away from the base substrate, and a plurality of openings being formed on the pixel defining layer, wherein the openings are provided in one-to-one correspondence with the sub-electrodes, and the first light- emitting layer is provided on a side of the pixel defining layer away from the first electrode layer, and an orthographic projection of the first light-emitting layer on the base substrate covers an orthographic projection of each of the openings on the base substrate, and orthographic projections of the second sub-light-emitting layer and the third light-emitting layer on the base substrate are within orthographic projections of the openings on the base substrate. Regarding claims 5 and 12, Heo et al. teach in figure 3 and related text (see e.g. paragraphs [003] and [0087]) a hole injection layer provided on the side of the first electrode layer away from the base substrate; a hole transport layer provided on a side of the hole injection layer away from the first electrode layer, wherein the first light-emitting layer is provided on a side of the hole transport layer away from the hole injection layer; an electron transport layer provided on a side of the first light-emitting layer, and the third light-emitting layer away from the connecting layer; and an electron injection layer provided on a side of the electron transport layer away from the first light-emitting layer, and the second electrode layer being provided on a side of the electron injection layer away from the electron transport layer. Regarding claims 6 and 13, Heo et al. teach in figure 3 and related text an electron blocking layer 250 provided on a side of the hole transport layer away from the hole injection layer, wherein the first light-emitting layer being provided on a side of the electron blocking layer away from the hole transport layer; a hole blocking layer provided on a side of the first light-emitting layer, the second light-emitting layer away from the electron blocking layer, wherein the electron transport layer being provided on a side of the hole blocking layer away from the second light-emitting layer and the third light-emitting layer. Regarding claim 7, it would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to provide a light extraction layer on a side of the second electrode layer away from the third light-emitting layer and an encapsulation layer on a side of the light extraction layer away from the second electrode layer in Heo et al.’s device, in order to improve the device characteristics and in order to provide better protection to the device, respectively. Regarding claim 8, it would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to use a HOMO energy level difference between the first light-emitting layer and the electron blocking layer is 0~0.3 eV, in Heo et al.’s device, in order to adjust the device characteristics. Regarding claims 9-10, it would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to use a hole mobility of the first light-emitting layer greater than or equal to 1x109 cm2/Vs and a hole mobility of the first common connection layer greater than or equal to 1x10-5 cm2/Vs, in Heo et al.’s device, in order to adjust the device characteristics. Regarding claim 11, Heo et al. teach in figure 3 and related text that the first light-emitting layer is a blue light-emitting layer, the second light-emitting layer is a green light-emitting layer, and the third light-emitting layer is a red light-emitting layer. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ORI NADAV whose telephone number is 571-272-1660. The examiner can normally be reached between the hours of 7 AM to 4 PM (Eastern Standard Time) Monday through Friday. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). O.N. /ORI NADAV/ 9/7/2026 PRIMARY EXAMINER TECHNOLOGY CENTER 2800
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Prosecution Timeline

Jul 19, 2024
Application Filed
Sep 10, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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DISPLAY APPARATUS
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Patent 12726559
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SEMICONDUCTOR DEVICE
3y 10m to grant Granted Sep 01, 2026
Patent 12720969
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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
60%
Grant Probability
81%
With Interview (+21.2%)
3y 9m (~1y 7m remaining)
Median Time to Grant
Low
PTA Risk
Based on 710 resolved cases by this examiner. Grant probability derived from career allowance rate.

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