Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-2, 4-6 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang (CN 112635486, hereinafter Zhang) in view of Choi et al. (US 2018/0366488, hereinafter Choi).
With respect to claim 1, Zhang discloses a method of manufacturing a memory device (Page 02; Para 02), the method comprising:
forming first openings (230 of Fig. 2a) passing through a first preliminary
stacked structure (220); forming sacrificial pillars (240/250 of Fig. 2b) filling the first openings; forming a second preliminary stacked structure (260 of Fig. 2c) over the first
preliminary stacked structure and the sacrificial pillars (Fig. 2c); forming first channel holes (280 of Fig. 2d) passing through the first preliminary stacked structure and the second preliminary stacked structure by removing a portion of the second preliminary stacked structure and the sacrificial pillars (Fig. 2d).
Zhang does not explicitly disclose forming cell plugs in the first channel holes.
In an analogous art, Choi discloses forming cell plugs in the first channel holes (Para 0020; 0035; Fig.1 - cell plugs). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Zhang’s device by having Choi’s disclosure in order to miniaturize the size of a memory device.
With respect to claim 2, Zhang discloses wherein in the forming of the first openings, each of the first openings has substantially a shape of a hole (30 of Fig. 2a).
With respect to claim 4, Zhang discloses wherein the forming of the first channel holes comprises: exposing the sacrificial pillars by etching the portion of the second preliminary stacked structure (Page 2; Para 01 & Page 04; Para 02); and removing exposed portions of the sacrificial pillars (Fig. 2d).
With respect to claim 5, Zhang discloses wherein in the forming of the first
channel holes, the sacrificial pillars are at least partially removed to expose an inner surface of the first preliminary stacked structure through the first openings (Fig. 2d).
With respect to claim 6, Zhang discloses wherein in the forming of the first
channel holes, each of the first channel holes has a tapered cross- section gradually decreasing toward a lower part (Fig. 2d).
With respect to claim 17, Zhang/Choi discloses the method of claim 1.
Zhang does not explicitly disclose wherein the forming of the cell
plug comprises: forming a memory layer in each of the first holes, the memory layer contacting the first preliminary stacked structure and the second preliminary stacked structure; and forming a channel layer on an inner surface of the memory layer.
In an analogous art, Choi discloses wherein the forming of the cell plug comprises: forming a memory layer in each of the first holes, the memory layer contacting the first preliminary stacked structure and the second preliminary stacked structure; and forming a channel layer on an inner surface of the memory layer (Para 0035; 0051-0052). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Zhang’s device by having Choi’s disclosure in order to miniaturize the size of a memory device.
Claims 3 and 7-14 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang/Choi in view of Hopkins et al. (US 2021/0013228, hereinafter Hopkins).
With respect to claim 3, Zhang/Choi discloses the method of claim 1.
Zhang/Choi does not explicitly disclose wherein the forming of the sacrificial pillars comprises filling the first openings with an insulating material.
In an analogous art, Hopkins discloses wherein the forming of the sacrificial pillars comprises filling the first openings with an insulating material (Para 0056 – high -k dielectric). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Zhang/Choi’s device by having Hopkin’s disclosure in order to isolate different component of a semiconductor device.
With respect to claim 7, Zhang/Choi discloses the method of claim 1.
Zhang/Choi does not explicitly disclose wherein the forming of the first openings is performed simultaneously with forming a second opening passing through the first preliminary stacked structure and having substantially a linear shape.
In an analogous art, Hopkins discloses wherein the forming of the first openings is performed simultaneously with forming a second opening passing through the first preliminary stacked structure and having substantially a linear shape (Fig. 13). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Zhang/Choi’s device by having Hopkin’s disclosure in order to expedite the manufacturing process of a semiconductor device.
With respect to claim 8, Zhang discloses wherein the forming of the
sacrificial pillars is performed simultaneously with forming a lower isolation structure filling the second opening (Page 07; Para 03; Page 11; last Para; Page 12; Para 01).
With respect to claim 9, Zhang/Choi discloses the method of claim 8.
Zhang/Choi does not explicitly disclose wherein the forming of the
sacrificial layers and the lower isolation structure comprises filling the first openings and the second opening with an insulating material.
In an analogous art, Hopkins discloses wherein the forming of the sacrificial layers and the lower isolation structure comprises filling the first openings and the second opening with an insulating material (Para 0056 and 0062). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Zhang/Choi’s device by having Hopkin’s disclosure in order to isolate different components of a semiconductor device.
With respect to claim 10, Zhang/Choi discloses the method of claim 8.
Zhang/Choi does not explicitly disclose wherein the forming of the first channel holes is performed simultaneously with forming second channel holes passing through the first preliminary stacked structure and the second preliminary stacked structure by removing the portion of the second preliminary stacked structure and a portion of the lower isolation structure.
In an analogous art, Hopkins discloses wherein the forming of the first channel holes is performed simultaneously with forming second channel holes passing through the first preliminary stacked structure and the second preliminary stacked structure by removing the portion of the second preliminary stacked structure and a portion of the lower isolation structure (Para 0056-0057; 0062; Fig. 8-13). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Zhang/Choi’s device by having Hopkin’s disclosure in order to isolate different components of a semiconductor device.
With respect to claim 11, Zhang/Choi discloses the method of claim 10.
Zhang/Choi does not explicitly disclose wherein in the forming of the first channel holes, the second channel holes pass through the lower isolation structure.
In an analogous art, Hopkins discloses wherein in the forming of the first channel holes, the second channel holes pass through the lower isolation structure (Fig. 9 -13). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Zhang/Choi’s device by having Hopkin’s disclosure in order to isolate different components of a semiconductor device to avoid short circuiting.
With respect to claim 12, Zhang/Choi discloses the method of claim 10.
Zhang/Choi does not explicitly disclose wherein in the forming of the second channel holes, an inner surface of the first preliminary stacked structure, an inner surface of the second preliminary stacked structure, and an inner surface of the lower isolation structure are exposed through the second channel holes.
In an analogous art, Hopkins discloses wherein in the forming of the second channel holes, an inner surface of the first preliminary stacked structure, an inner surface of the second preliminary stacked structure, and an inner surface of the lower isolation structure are exposed through the second channel holes (Fig. 13).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Zhang/Choi’s device by having Hopkin’s disclosure in order to isolate different components of a semiconductor device to avoid short circuiting.
With respect to claim 13, Zhang/Choi discloses the method of claim 8.
Zhang/Choi does not explicitly disclose wherein the forming of the first
channel holes is performed simultaneously with forming second channel holes into at least a portion of the first preliminary stacked structure and passing through the second preliminary stacked structure by removing the portion of the second preliminary structure and a portion of the lower isolation structure.
In an analogous art, Hopkins discloses wherein the forming of the first channel holes is performed simultaneously with forming second channel holes into at least a portion of the first preliminary stacked structure and passing through the second preliminary stacked structure by removing the portion of the second preliminary structure and a portion of the lower isolation structure (Para 0056-0057; 0062; Fig. 8-13). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Zhang/Choi’s device by having Hopkin’s disclosure in order to isolate different components of a semiconductor device to protect the device.
With respect to claim 14, Zhang/Choi/Hopkins discloses the method of claim 13.
Zhang/Choi does not explicitly disclose wherein in the forming of the
first channel holes, the second channel holes are formed into at least a portion of the lower isolation structure.
In an analogous art, Hopkins discloses wherein in the forming of the
first channel holes, the second channel holes are formed into at least a portion of the lower isolation structure (Figs. 9-13).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Zhang/Choi’s device by having Hopkin’s disclosure in order to isolate different components of a semiconductor device to protect the device.
Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang/Choi in view of Won (KR 1020210143976, hereinafter Won).
With respect to claim 15, Zhang/Choi discloses the method of claim 1.
Zhang/Choi does not explicitly disclose before forming the first openings, forming the first preliminary stacked structure by stacking at least one first material layer and at least one second material layer.
In an analogous art, Won discloses before forming the first openings (Figs. 6-7 & 10), forming the first preliminary stacked structure (Fig. 6) by stacking at least one first material layer (62) and at least one second material layer (63).Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Zhang/Choi’s device by having Won’s disclosure in order to miniaturize the size of a memory device.
With respect to claim 16, Zhang/Choi/Won discloses the method of claim 15.
Zhang discloses wherein the forming of the second preliminary stacked structure comprises alternately stacking third material layers and fourth material layers over the first preliminary stacked structure (Fig. 2c – stack 260 comprises of alternate layer), wherein the third material layers include a same material as the first material layer, and wherein the fourth material layers include a same material as the second material layer (Page06; Para 01; Page 07; Para 01; and Page 09; Para 02).
Conclusion
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/MOHAMMAD M CHOUDHRY/Primary Examiner, Art Unit 2899
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