DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed on 07/19/2024 has been considered.
Drawings
The drawings filed on 07/19/2024 are acceptable.
Specification
The abstract of the disclosure and the specification filed on 07/19/2024 are acceptable.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 10, 12-15, 17, 19 and 21 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Yap. (US 2015/0333028).
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Regarding claim 10, Yap (US 2015/0333028) discloses:
A method of fabricating a wafer chip-scale package (WCSP), comprising:
providing a substrate (52, ¶0021) comprising a semiconductor surface layer including circuitry configured for at least one function having at least a top metal interconnect layer thereon that includes at least one bond pad (57, ¶0021) coupled to a node in the circuitry (0021);
forming a passivation layer (58, 62, ¶0021) over the top metal interconnect layer (57);
forming a masking pattern on the passivation layer (¶0021);
utilizing the masking pattern, forming a metal RDL (“patterned metal level”, ¶0013, ¶0021) including a bump pad (76, ¶0022) that is coupled by a trace (60, ¶0021) to the bond pad (57);
additively printing a dielectric ring comprising a dielectric material (68, ¶0023) on the bump pad (76), the dielectric ring having an inner area sized for receiving a solder ball (¶0016), and
dropping the solder ball on the bump pad including within the dielectric ring so that the inner area of the dielectric ring is in physical contact with the solder ball (¶0021).
Regarding claim 12, Yap further discloses:
wherein the additively printing comprises inkjet printing of the dielectric material (¶0023).
Regarding claim 13, Yap further discloses:
wherein the dielectric ring comprises a solder resist material (¶0023).
Regarding claim 14, Yap further discloses:
wherein the dielectric ring comprises an epoxy-based material (¶0023).
Regarding claim 15, Yap further discloses:
wherein after the dropping the solder ball the solder ball (66) is in direct contact with the bump pad (76).
Regarding claim 17, Yap further discloses:
wherein the dielectric ring (68, also shown as dashed circle 78 in figure 6, ¶0022) is a fully continuous ring.
Regarding claim 19, Yap further discloses:
wherein the dielectric ring is 2 µm to 25 µm thick (¶0023).
Regarding claim 21, Yap further discloses:
wherein the forming of the masking pattern comprises photolithography (¶0013 discloses patterning).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yap.
Regarding claim 18, Yap does not disclose:
wherein the dielectric ring comprises a plurality of segments that are spaced apart from one another. However, a change in size or shape or both is an unpatentable modification when it results in optimum conditions that differ from the prior art in degree but not in kind. In Re Rose, 220 F.2d 459, 105 USPQ 237, In reDailey, 357 F.2d 669, 149 USPQ 47). In the instant case the prior art method would not execute differently if modified to the claimed shape or size. Therefore, the claimed limitations are considered met.
Claim(s) 20, 22, 24-26, 28-30 and 32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ji (US 2017/0162540).
Regarding claim 20, Yap does not disclose “forming metal full plugs through the passivation layer for coupling the trace to the bond pad”.
In a similar device, however, Ji (US 2017/0162540, figures 9 and 10) discloses a method of forming package (¶0034) including forming a substrate (200, ¶0023) comprising a semiconductor surface layer including circuitry configured for at least one function having at least a top metal interconnect layer thereon (¶0018) that includes at least one bond pad (202, ¶0023), coupled to a node in the circuitry (¶0018), providing a redistribution layer (RDL) (212, ¶0033) including a bump pad (in figures 9 and 10, the surface of RDL 212 that is exposed by the opening 216, ¶0028) coupled by a trace (212) extending between opening (216) and the openings in passivation layer (204a) coupled to metal filled plugs (212a, ¶0027) through a passivation layer (204a,¶0027) to the bond pad (202). Ji discloses that method as taught provides an RDL with improved characteristics (0027, ¶0030). Therefore, it would have been obvious to one having skill in the art before the effective filing date of the claimed invention to modify the method of Chen, including forming a redistribution layer including a bump pad coupled by a trace coupled to metal filled plugs through a passivation layer to the bond pad, in order to provide an improved RDL as taught by Ji.
Regarding claim 22, Yap discloses:
A method, comprising:
forming circuitry (die 54, ¶0021) having at least a top metal interconnect layer thereon that includes at least one bond pad (57) coupled to a node in the circuitry (¶0021);
forming a redistribution layer (RDL) including a bump pad (76) coupled by a trace (60) coupled to the bond pad (57);
forming a solder ball (66) on the bump pad (76), and
forming a dielectric ring (68) on a same surface of the bump pad (76) as the solder ball (66), the dielectric ring (68) having an inner area in physical contact with the solder ball (66).
Yap does not disclose “forming a redistribution layer (RDL) including a bump pad coupled by a trace coupled to metal filled plugs through a passivation layer to the bond pad”.
In a similar device, however, Ji (US 2017/0162540, figures 9 and 10) discloses a method of forming package (¶0034) including forming a substrate (200, ¶0023) comprising a semiconductor surface layer including circuitry configured for at least one function having at least a top metal interconnect layer thereon (¶0018) that includes at least one bond pad (202, ¶0023), coupled to a node in the circuitry (¶0018), providing a redistribution layer (RDL) (212, ¶0033) including a bump pad (in figures 9 and 10, the surface of RDL 212 that is exposed by the opening 216, ¶0028) coupled by a trace (212) extending between opening (216) and the openings in passivation layer (204a) coupled to metal filled plugs (212a, ¶0027) through a passivation layer (204a,¶0027) to the bond pad (202). Ji discloses that method as taught provides an RDL with improved characteristics (0027, ¶0030). Therefore, it would have been obvious to one having skill in the art before the effective filing date of the claimed invention to modify the method of Chen, including forming a redistribution layer including a bump pad coupled by a trace coupled to metal filled plugs through a passivation layer to the bond pad, in order to provide an improved RDL as taught by Ji.
Regarding claim 24, Yap further discloses:
wherein the additively printing comprises inkjet printing of the dielectric material (¶0023).
Regarding claim 25, Yap further discloses:
wherein the dielectric ring comprises a solder resist material (¶0023).
Regarding claim 26, Yap further discloses:
wherein the dielectric ring comprises an epoxy-based material (¶0023).
Regarding claim 28, the modification of Ji further discloses:
wherein the trace (212) is coupled to the metal filled plugs (212a) through the passivation layer (204a) to the bump pad (¶0028).
Regarding claim 29, Yap further discloses:
wherein the dielectric ring (68, also shown as dashed circle 78 in figure 6, ¶0022) is a fully continuous ring.
Regarding claim 30, Yap in view of Ji does not disclose “wherein the dielectric ring comprises a plurality of segments that are spaced apart from one another”. However, a change in size or shape or both is an unpatentable modification when it results in optimum conditions that differ from the prior art in degree but not in kind. In Re Rose, 220 F.2d 459, 105 USPQ 237, In reDailey, 357 F.2d 669, 149 USPQ 47). In the instant case the prior art method would not execute differently if modified to the claimed shape or size. Therefore, the claimed limitations are considered met.
Regarding claim 32, Yap further discloses:
wherein the apparatus is a wafer chip-scale package (WCSP) (abstract).
Allowable Subject Matter
Claims 11, 16, 23, 27, 31 objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 11, the prior art does not disclose “forming a mold material including over the dielectric ring and in physical contact with the solder ball” in combination with the remaining claimed features.
Regarding claim 23, the prior art does not disclose “forming a re-passivation layer comprising a mold material including over the dielectric ring and in contact with the solder ball” in combination with the remaining claimed features.
Regarding claim 27, the prior art does not disclose “forming a re-passivation layer comprising a mold material including over the dielectric ring and in contact with the solder ball, wherein the substrate includes at least one trench therein that has a depth that is at least 10% of a thickness of the substrate, and wherein the mold material is also within the trench” in combination with the remaining claimed features.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM A HARRISTON whose telephone number is (571)270-3897. The examiner can normally be reached Mon-Fri, 9AM-5PM.
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/WILLIAM A HARRISTON/ Primary Examiner, Art Unit 2899
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