DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to application filed on 07/19/2024.
Currently claims 1-20 are pending in the application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/19/2024 was filed before the mailing date of the office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement was considered by the examiner.
Claim Objections
Claim 18 is objected to because of the following informalities:
Regarding claim 18, in the limitation “and is connected to a contact plug of among the plurality of contact plugs” (claim 18, lines 8-9), the phrase “of among” appears to be a grammatical error. It is suggested that the phrase be amended to recite —a contact plug from among the plurality of contact plugs …or … a contact plug of the plurality of contact plugs ….
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 4 and 6-10 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0247821 A1 (Kwon) in view of US 2022/0216239 A1 (Yoo), and further in view of US 2019/0280090 A1 (Stephenson).
Regarding claim 1, Kwon discloses, a semiconductor memory device (semiconductor device 100 showing a memory cell having a 4F2 structure, including a bit line, a vertical channel transistor and a capacitor; Figs. 1-2C; [0024]-[0025]) comprising:
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a conductive line extending in a first direction (the bit line 103 extend laterally in a first direction D1 over the buffer layer 102; [0028]; Fig. 1);
a plurality of channel areas spaced apart from each other in the first direction on the conductive line and each connected to the conductive line (a plurality of semiconductor pillars 104/14P, each including a vertical channel extending in the third direction D3, are disposed over the bit lines and are spaced apart from each other along the first direction D1 — see the memory cell arrays MCA1, MCA2, and MCA3 spaced apart from each other in the first direction D1, each including semiconductor pillars over the shared bit lines 103; each pillar is electrically connected to the bit line through the lower doped layer 109/19 and the ohmic contact layer 111/20; [0005], [0025], [0030]-[0031], [0039]-[0040], [0062]; Figs. 1, 2A-2C, 12);
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a back-gate electrode extending in a second direction between a first channel area and a second channel area of the plurality of channel areas, the first channel area and the second channel area being adjacent to each other (the body line 106/30 extends laterally in the second direction D2 and is disposed in a trench between neighboring semiconductor pillars, directly coupled to a first sidewall SW1 of a semiconductor pillar; a body bias Vbb may be applied through the body line, i.e., the body line functions as a back-gate electrode for the vertical channel; [0032]-[0034], [0065]-[0070]; Figs. 2A-2C, 14-17),
wherein the back-gate electrode is spaced apart from the conductive line in a third direction (the body line is spaced apart from the bit line 22 in the vertical direction D3; a portion of the third dielectric line 28 is disposed between the body-line trench 29 and the bit line 22, and the bottom surface of the body line is disposed at the same lateral level as the bottom surface of the vertical word line, above the bit line; [0033], [0065]; Figs. 2B, 14),
wherein the second direction is perpendicular to the first direction (the vertical word lines 105 and the body lines 106 extend laterally in the second direction D2 and cross the bit lines 103 extending in the first direction D1; [0032]; Fig. 2A); and
a word line arranged between the second channel area and a third channel area of the plurality of channel areas, the second channel area and the third channel area being adjacent to each other (a vertical word line 105/35 extends in the second direction D2 in a trench between neighboring semiconductor pillars, over a second sidewall SW2 of the semiconductor pillar with a gate dielectric layer 107/34 interposed therebetween; the body lines 106 are disposed between the neighboring vertical word lines 105 in the first direction D1, i.e., the body lines and the vertical word lines alternate along the first direction with the pillars therebetween; [0032]-[0033], [0043], [0073]-[0076]; Figs. 2A-2C, 18).
But Kwon fails to teach explicitly, a pair of word lines arranged between the second channel area and the third channel area, wherein the pair of word lines are spaced apart from each other in the first direction (Kwon's illustrated arrangement has a single vertical word line 105 disposed between adjacent semiconductor pillars; [0032]-[0033]); and a superlattice layer disposed on the conductive line, wherein the superlattice layer comprises a first superlattice layer comprising a plurality of first oxide layers and a plurality of first compound layers that are alternately stacked on each other, and wherein the superlattice layer comprises a second superlattice layer comprising a plurality of second oxide layers and a plurality of second compound layers that are alternately stacked on each other.
However, in analogous art, Yoo discloses, a semiconductor memory device in which bit lines, cell transistors, and capacitors are vertically stacked, including an embodiment in which the interconnection layer ICL (bit lines), the selection element layer SL, and the data storage layer DSL are sequentially stacked in the third direction (Figs. 2-3; [0035]-[0038]), wherein a pair of the word lines WL is disposed to cross the first and second channel regions CH1 and CH2 of each active pattern, such that the first channel region CH1 is controlled by a first word line and the second channel region CH2 is controlled by a second word line ([0062]), the pair of word lines being spaced apart from each other in the direction of bit line extension with a bit line contact plug DC provided between the pair of the word lines ([0007]-[0008], [0062]-[0063]; Figs. 4, 5A), whereby each of two adjacent channel regions is independently controlled by a respective word line of the pair.
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Kwon and Yoo before him/her, to modify the teachings of a semiconductor memory device having vertical channel transistors as taught by Kwon and to include the teachings of a pair of word lines that are spaced apart from each other in the first direction between two adjacent channel areas, each word line of the pair controlling a respective one of the adjacent channel areas, as taught by Yoo, since providing each of the two channel areas flanking a shared inter-pillar region with its own word line permits the adjacent memory cells to be accessed independently of one another while sharing a single inter-pillar region, thereby increasing integration density and operational flexibility with predictable results, and since such a modification amounts to no more than a mere duplication of Kwon's vertical word line with a corresponding gate dielectric for the facing sidewall of the neighboring pillar (see MPEP 2144.04(VI)(B)). Absent this important teaching in Kwon, a person with ordinary skill in the art would be motivated to reach out to Yoo while forming a semiconductor memory device of Kwon.
But the combination of Kwon and Yoo fails to teach explicitly, a superlattice layer disposed on the conductive line, the plurality of channel areas being disposed on the superlattice layer, wherein the superlattice layer comprises a first superlattice layer comprising a plurality of first oxide layers and a plurality of first compound layers that are alternately stacked on each other, and wherein the superlattice layer comprises a second superlattice layer comprising a plurality of second oxide layers and a plurality of second compound layers that are alternately stacked on each other.
However, in analogous art, Stephenson discloses, a semiconductor device including an enhanced contact structure having a superlattice disposed between a semiconductor material and a conductive body (superlattice/MST film 25 lining a contact region, with a conductive body including a Ti/TiN liner 36, a tungsten fill 37, and a silicide 40 thereon; [0013]-[0014], [0057]-[0058]; Figs. 5-8), wherein the superlattice 25 includes a plurality of stacked groups of layers 45a-45n, each group of layers including a plurality of stacked base silicon monolayers 46 defining a base semiconductor portion and an energy band-modifying layer 50 comprising at least one oxygen (non-semiconductor) monolayer constrained within a crystal lattice of adjacent base semiconductor portions, i.e., oxygen-containing (oxide) layers alternately stacked with silicon-based layers ([0040]-[0045]; Figs. 1-2); the superlattice may further comprise at least one type of conductivity dopant therein ([0048]), and the contact region including the superlattice film is implanted with a dopant including one or more of boron, arsenic, and phosphorus such that the doped superlattice layer holds and constrains the dopants, i.e., the silicon-based layers of the doped superlattice are phosphorus-containing silicon (SiP) layers and/or arsenic-containing silicon (SiAs) layers as interpreted above under the broadest reasonable interpretation ([0057], [0061], [0063]); the superlattice may include a first superlattice layer and a second superlattice layer arranged thereon having different numbers of base monolayers, for example a repeating 3/1/5/1 pattern in which the lowest base semiconductor portion has three monolayers and the second lowest base semiconductor portion has five monolayers ([0049]-[0050]; Fig. 3); and the superlattice acts as a barrier to dopant and/or material diffusion, constraining the contact dopants in place during subsequent thermal steps while supporting low-resistance silicide/ohmic contact formation ([0045], [0057]-[0063]; Figs. 5-9).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Kwon, Yoo and Stephenson before him/her, to modify the teachings of a semiconductor memory device as taught by the combination of Kwon and Yoo and to include the teachings of a superlattice contact film comprising alternately stacked oxygen (oxide) monolayers and doped silicon compound layers, including a first superlattice layer and a second superlattice layer stacked on the first superlattice layer, disposed at the contact interface between the bit line and the overlying doped contact and channel areas, as taught by Stephenson, since Stephenson's superlattice contact film constrains the N-type contact dopants of Kwon's lower doped layers 19 in place during subsequent thermal processing steps, acts as a dopant diffusion barrier that maintains a shallow and abrupt contact junction, and is compatible with the metal silicide ohmic contact formation employed by Kwon, thereby reducing contact resistance and junction leakage of the bit line contact with predictable results. Absent this important teaching in Kwon, a person with ordinary skill in the art would be motivated to reach out to Stephenson while forming the bit line contact of the semiconductor memory device of Kwon.
Regarding claim 2, the combination of Kwon, Yoo and Stephenson discloses, the semiconductor memory device of claim 1, wherein the second superlattice layer is arranged on the first superlattice layer (Stephenson Ref: in the repeating 3/1/5/1 superlattice pattern, the second lowest group of layers, having five base monolayers and an oxygen monolayer, is arranged on the lowest group of layers, having three base monolayers and an oxygen monolayer, and this pattern repeats throughout the superlattice; [0049]-[0050]; Fig. 3).
Regarding claim 4, the combination of Kwon, Yoo and Stephenson discloses, the semiconductor memory device of claim 1, wherein a thickness of the superlattice layer in the third direction is in a range of about 1 nm to about 100 nm (Stephenson Ref: the superlattice is formed of stacked groups of atomic monolayers, each group being, e.g., three to five silicon monolayers together with an oxygen monolayer, with a semiconductor cap layer of between 2 to 100 monolayers, such that the overall superlattice film is of nanometer-scale thickness within the claimed range (average thickness of a monolayer is typically in the 0.3–1.7 nm range); [0040]-[0041], [0046]-[0047], [0049]). Moreover, the thickness of the superlattice contact film is a result-effective variable directly affecting the dopant-blocking capability and the contact resistance of the contact structure ([0057]-[0063]), and it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to arrive at the claimed thickness range through routine experimentation and optimization, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art (MPEP 2144.05(II)).
Regarding claim 6, the combination of Kwon, Yoo and Stephenson discloses, the semiconductor memory device of claim 1, wherein a concentration of phosphorus (P) included in the first compound layer is in a range of about 10¹⁶/cm³ to about 10²²/cm³ (Stephenson: the contact region including the superlattice film is implanted with a dopant including phosphorus at conventional contact-implant energies and doses, the doped superlattice layer retaining a high contact dopant dosage; [0057], [0063]; contact doping concentrations that provide ohmic contact conduction necessarily fall within the broadly claimed range spanning six orders of magnitude). Furthermore, it would have been obvious to one of ordinary skill in the art to arrive at the claimed phosphorus concentration range through routine optimization of the contact implant dose in order to obtain the desired contact resistance (MPEP 2144.05(II)).
Regarding claim 7, the combination of Kwon, Yoo and Stephenson discloses, the semiconductor memory device of claim 1, wherein a concentration of arsenic (As) included in the second compound layer is in a range of about 10¹⁶/cm³ to about 10²²/cm³ (Stephenson: the contact region including the superlattice film is implanted with a dopant including arsenic; [0057], [0063]; the same reasoning and routine-optimization rationale set forth above with respect to claim 6 applies (MPEP 2144.05(II))).
Regarding claim 8, the combination of Kwon, Yoo and Stephenson discloses, the semiconductor memory device of claim 1, wherein the first oxide layer and the second oxide layer comprise a same material (Stephenson: each group of layers of the superlattice, including the lowest (first) group and the second lowest (second) group of the 3/1/5/1 repeating pattern, includes an energy band-modifying layer comprising an oxygen monolayer, i.e., the oxide layers of the first superlattice layer and of the second superlattice layer are of the same material; [0041]-[0042], [0045], [0049]).
Regarding claim 9, the combination of Kwon, Yoo and Stephenson discloses, the semiconductor memory device of claim 1, further comprising a metal silicide film between the superlattice layer and the conductive line (Kwon: the ohmic contact layer 111/20 comprising a metal silicide, e.g., titanium silicide or cobalt silicide, is disposed between the lower doped layer 109/19 and the bit line 103/22; [0025], [0029]-[0030], [0053]-[0054]; Figs. 2B, 7-9; Stephenson: the silicide 40 is formed on the conductive-body side of the superlattice film, such that the resulting stack is silicide 40 / heavily doped silicon / doped MST (superlattice) layer; [0058]-[0061]; Figs. 6-8; in the combination, the metal silicide film is located between the superlattice layer and the conductive line).
Regarding claim 10, the combination of Kwon, Yoo and Stephenson discloses, the semiconductor memory device of claim 1, further comprising a plurality of contact plugs spaced apart from the conductive line in the third direction, wherein the plurality of channel areas are respectively arranged between the plurality of contact plugs and the conductive line, and wherein each contact plug of the plurality of contact plugs is in contact with a channel area of the plurality of channel areas (Kwon: conductive upper doped layers 110/37 are formed in and over the upper regions of the semiconductor pillars, respectively, in contact with the respective pillars, and the capacitor lower electrodes contact the upper doped layers; the upper doped layers are spaced apart from the bit line in the vertical direction D3 with the channel areas therebetween; [0025], [0031], [0078]-[0080], [0098]-[0099]; Figs. 2B, 19-20, 24), and
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wherein the back-gate electrode has a first end surface that faces the plurality of contact plugs and a second end surface that faces the superlattice layer and the conductive line (Kwon: the body line 106/30 is a vertically extending line whose top (first end) surface is disposed at a level facing the upper doped layers/capacitors and whose bottom (second end) surface is disposed at a level facing the bit line; [0033]; Figs. 2B-2C; in the combination with Stephenson, the bottom end surface faces the superlattice layer disposed on the bit line).
Claims 12-15 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0247821 A1 (Kwon) in view of US 2020/0295008 A1 (Tang), and further in view of US 2019/0280090 A1 (Stephenson).
Regarding claim 12, Kwon discloses, a semiconductor memory device (semiconductor device 100; Figs. 1-2C; [0024]-[0025]) comprising:
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a conductive line extending in a first direction (bit line 103 extending laterally in the first direction D1; [0028]);
a plurality of channel areas spaced apart from each other in the first direction, wherein the plurality of channel areas are spaced apart from the conductive line in a third direction (semiconductor pillars 104/14P spaced apart from each other along the first direction D1 over the bit lines, each pillar being separated from the bit line in the vertical direction D3 by the lower doped layer 109/19 and the ohmic contact layer 111/20; [0025], [0030]-[0031], [0039]-[0040], [0062]; Figs. 1-2C);
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a plurality of contact plugs spaced apart from the conductive line in the third direction, wherein the plurality of channel areas are respectively arranged between the plurality of contact plugs and the conductive line (upper doped layers 110/37 respectively on the semiconductor pillars, contacted by the capacitors 108/38; [0025], [0031], [0078]-[0080], [0098]-[0099]);
a back-gate electrode extending in a second direction between a first channel area and a second channel area of the plurality of channel areas, the first channel area and the second channel area being adjacent to each other, wherein the back-gate electrode is spaced apart from the conductive line in the third direction, and wherein the second direction is perpendicular to the first direction (body line 106/30 extending in the second direction D2 between neighboring semiconductor pillars, crossing the bit line, and spaced apart from the bit line in the vertical direction; [0032]-[0034], [0043], [0065]-[0070]; Figs. 2A-2C);
a word line spaced apart from the back-gate electrode in the first direction, wherein the second channel area is arranged between the word line and the back-gate electrode (the vertical word line 105/35 and the body line 106/30 face each other with the semiconductor pillar 104/14P interposed therebetween; [0033], [0076]; Figs. 2A-2B); and
a gate dielectric film arranged between the word line and the second channel area and contacting each of the word line and the second channel area (gate dielectric layer 107/34 interposed between the vertical word line and the sidewall of the semiconductor pillar; [0033], [0036], [0073]-[0074]).
But Kwon fails to teach explicitly, a back-gate dielectric film arranged between the back-gate electrode and the second channel area and contacting each of the back-gate electrode and the second channel area (Kwon's body line has a pillar-tied or body-tied structure in which the body line directly contacts the sidewall of the semiconductor pillar; [0033], [0087]); and a superlattice layer disposed on the conductive line, wherein the superlattice layer has a structure in which a plurality of oxide layers and a plurality of compound layers are alternately stacked on each other.
However, in analogous art, Tang discloses, an integrated assembly of vertically-extending memory cells (e.g., DRAM cells) in which the first and second diffusion regions and the channel region of each access device are arranged vertically, a word line is adjacent a first side surface of the channel region, and a conductive shield plate (43) is adjacent an opposing second side surface of the channel region (Figs. 21A-22B; [0103] – [0104]), wherein trenches extending between rows of the memory cells are lined with an insulative material 40 and a conductive shield material 42 is formed within the lined trenches such that the shield material is electrically isolated from the body/channel regions of the memory cells by the insulative material 40, the insulative material 40 contacting each of the shield material 42 and the semiconductor body regions (Figs. 21A-22B, 24A-24B; [0103] – [0115]), and wherein Tang expressly discloses that the shielding material may directly contact the body regions of the memory cells in some embodiments, and may be electrically isolated from the body regions of the memory cells in other embodiments (Figs. 21-24; [0106], [0110] – [0112]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Kwon and Tang before him/her, to modify the teachings of a semiconductor memory device as taught by Kwon and to include the teachings of a dielectric film interposed between the body-side electrode and the channel area and contacting each of them, as taught by Tang, since Tang teaches that a conductive shield/body-side electrode disposed between adjacent vertical memory cells may either directly contact the channel body regions or be electrically isolated therefrom by an intervening insulative liner, such that employing the dielectric-isolated configuration in Kwon is a simple substitution of one known, art-recognized configuration for another, yielding the predictable result of a biased back-side electrode that shields the adjacent cells and word lines from capacitive coupling and disturbance while avoiding a direct leakage path between the electrode and the channel. Absent this important teaching in Kwon, a person with ordinary skill in the art would be motivated to reach out to Tang while forming a semiconductor memory device of Kwon.
But the combination of Kwon and Tang fails to teach explicitly, a superlattice layer disposed on the conductive line, wherein the superlattice layer has a structure in which a plurality of oxide layers and a plurality of compound layers are alternately stacked on each other.
However, in analogous art, Stephenson discloses, a superlattice contact film disposed between a semiconductor material and a conductive body, the superlattice including a plurality of stacked groups of layers each having a plurality of stacked base silicon monolayers and at least one oxygen (non-semiconductor) monolayer constrained within the crystal lattice of adjacent base semiconductor portions, i.e., a structure in which oxide layers and doped-silicon compound layers are alternately stacked on each other, the contact region being implanted with a dopant including one or more of boron, arsenic, and phosphorus, and the superlattice acting as a dopant diffusion barrier compatible with silicide-based ohmic contacts ([0013]-[0014], [0040]-[0045], [0048]-[0050], [0057]-[0063]; Figs. 1-3, 5-8).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Kwon, Tang and Stephenson before him/her, to modify the teachings of a semiconductor memory device as taught by the combination of Kwon and Tang and to include the teachings of a superlattice contact film of alternately stacked oxide layers and doped silicon compound layers disposed at the contact interface between the bit line and the overlying doped contact and channel areas, as taught by Stephenson, since Stephenson's superlattice contact film constrains the N-type contact dopants of Kwon's lower doped layers in place during subsequent thermal processing steps, acts as a dopant diffusion barrier maintaining a shallow and abrupt contact junction, and is compatible with the metal silicide ohmic contact formation employed by Kwon, thereby reducing contact resistance and junction leakage of the bit line contact with predictable results. Absent this important teaching in Kwon, a person with ordinary skill in the art would be motivated to reach out to Stephenson while forming the bit line contact of the semiconductor memory device of Kwon.
Regarding claim 13, the combination of Kwon, Tang and Stephenson discloses, the semiconductor memory device of claim 12, wherein the plurality of compound layers comprise silicon phosphide (SiP), and a concentration of phosphorus (P) included in the plurality of compound layers is in a range of about 10¹⁶/cm³ to about 10²²/cm³ (Stephenson Ref: the contact region including the superlattice film is implanted with a dopant including phosphorus, the doped superlattice layer retaining a high contact dopant dosage, i.e., phosphorus-containing silicon (SiP) layers under the broadest reasonable interpretation set forth above; [0057], [0061], [0063]; contact doping concentrations providing ohmic conduction fall within the broadly claimed six-order-of-magnitude range, and it would at least have been obvious to arrive at the claimed range through routine optimization of the contact implant dose to obtain the desired contact resistance (MPEP 2144.05(II))).
Regarding claim 14, the combination of Kwon, Tang and Stephenson discloses, the semiconductor memory device of claim 12, wherein the plurality of compound layers comprise silicon arsenide (SiAs), and a concentration of arsenic (As) included in the plurality of compound layers is in a range of about 10¹⁶/cm³ to about 10²²/cm³ (Stephenson: the dopant may include arsenic; [0057], [0063]; the same broadest-reasonable-interpretation and routine-optimization rationale set forth above with respect to claim 13 applies (MPEP 2144.05(II))).
Regarding claim 15, the combination of Kwon, Tang and Stephenson discloses, the semiconductor memory device of claim 1, wherein a thickness of the superlattice layer in the third direction is in a range of about 1 nm to about 100 nm (Stephenson Ref: the superlattice is formed of stacked groups of atomic monolayers, each group being, e.g., three to five silicon monolayers together with an oxygen monolayer, with a semiconductor cap layer of between 2 to 100 monolayers, such that the overall superlattice film is of nanometer-scale thickness within the claimed range (average thickness of a monolayer is typically in the 0.3–1.7 nm range); [0040]-[0041], [0046]-[0047], [0049]). Moreover, the thickness of the superlattice contact film is a result-effective variable directly affecting the dopant-blocking capability and the contact resistance of the contact structure ([0057]-[0063]), and it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to arrive at the claimed thickness range through routine experimentation and optimization, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art (MPEP 2144.05(II)).
Regarding claim 17, the combination of Kwon, Tang and Stephenson discloses, the semiconductor memory device of claim 12, further comprising a metal silicide film between the superlattice layer and the conductive line (Kwon: ohmic contact layer 111/20 comprising titanium silicide or cobalt silicide between the lower doped layer and the bit line; [0029]-[0030], [0053]-[0054]; Stephenson: silicide 40 formed on the conductive-body side of the superlattice film; [0058]-[0061]; in the combination, the metal silicide film is located between the superlattice layer and the conductive line).
Claims 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0247821 A1 (Kwon) in view of US 2020/0295008 A1 (Tang), and further in view of US 2019/0280090 A1 (Stephenson).
Regarding claim 18, Kwon discloses, a semiconductor memory device (Figs. 1-2C; [0024]-[0025]) comprising:
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a plurality of conductive lines extending in a first direction and spaced apart from each other in a second direction that is perpendicular to the first direction (a plurality of bit lines 103/22 extending in the first direction D1, the neighboring bit lines being isolated from each other by the first and second dielectric lines 24 and 26 and spaced apart in the direction crossed by the vertical word lines; [0028], [0040], [0054]-[0065]; Figs. 2A, 9-12);
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a plurality of contact plugs spaced apart from the plurality of conductive lines in a third direction (upper doped layers 110/37, contacted by the capacitor lower electrodes 122, spaced apart from the bit lines in the vertical direction D3; [0025], [0031], [0077]-[0080], [0098]-[0099]; Figs. 2, 19);
a plurality of channel areas respectively arranged between the plurality of conductive lines and the plurality of contact plugs, wherein each channel area of the plurality of channel areas comprises an end that is spaced apart from the plurality of conductive lines in the third direction and is connected to a contact plug of among the plurality of contact plugs (semiconductor pillars 104/14P vertically interposed between the bit lines and the upper doped layers, the upper end of each pillar being connected to a respective upper doped layer; [0025], [0031], [0077]-[0079]; Figs. 2, 19);
a plurality of back-gate electrodes extending in the second direction between the plurality of conductive lines and the plurality of contact plugs and spaced apart from each other in the first direction (body lines 106/30 extending in the second direction D2, disposed vertically between the level of the bit lines and the level of the upper doped layers, and spaced apart from each other in the first direction D1; [0032]-[0034], [0043]; Figs. 2A-2C, 19);
a plurality of word lines extending in the second direction between the plurality of conductive lines and the plurality of contact plugs (vertical word lines 105/35 extending in the second direction D2, disposed vertically between the level of the bit lines and the level of the upper doped layers; [0032], [0074]-[0076]; Figs. 2A-2C, 19); and
a plurality of gate dielectric films respectively contacting the plurality of word lines (gate dielectric layers 107/34 respectively interposed between the vertical word lines and the semiconductor pillars; [0033], [0036], [0073]-[0074]; Figs. 2A-2C, 19).
But Kwon fails to teach explicitly, a plurality of back-gate dielectric films respectively contacting the plurality of back-gate electrodes (Kwon's body lines directly contact the sidewalls of the semiconductor pillars; [0033], [0087]); and a superlattice layer arranged between the plurality of channel areas and the plurality of conductive lines, wherein the superlattice layer has a structure in which a plurality of oxide layers and a plurality of compound layers are alternately stacked on each other, and the plurality of compound layers comprise a material selected from among silicon phosphide (SiP), silicon arsenide (SiAs), and a combination of SiP and SiAs.
However, in analogous art, Tang discloses, vertically-extending memory cells in which a conductive shield material 42 disposed in trenches between the memory cells is lined by, and in contact with, an insulative material 40 which electrically isolates the shield material from the body/channel regions of the memory cells (Figs. 21A-22B, 24A-24B; [0103] – [0115]; the shielding material may be electrically isolated from the body regions of the memory cells; Figs. 21-24; [0106], [0110] – [0112]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Kwon and Tang before him/her, to modify the teachings of a semiconductor memory device as taught by Kwon and to include the teachings of a plurality of dielectric films respectively contacting the plurality of body-side (back-gate) electrodes, as taught by Tang, Tang teaches that a conductive shield/body-side electrode disposed between adjacent vertical memory cells may either directly contact the channel body regions or be electrically isolated therefrom by an intervening insulative liner, such that employing the dielectric-isolated configuration in Kwon is a simple substitution of one known, art-recognized configuration for another, yielding the predictable result of a biased back-side electrode that shields the adjacent cells and word lines from capacitive coupling and disturbance while avoiding a direct leakage path between the electrode and the channel. Absent this important teaching in Kwon, a person with ordinary skill in the art would be motivated to reach out to Tang while forming a semiconductor memory device of Kwon.
But the combination of Kwon and Tang fails to teach explicitly, the superlattice layer arranged between the plurality of channel areas and the plurality of conductive lines, wherein the superlattice layer has a structure in which a plurality of oxide layers and a plurality of compound layers are alternately stacked on each other, and the plurality of compound layers comprise a material selected from among silicon phosphide (SiP), silicon arsenide (SiAs), and a combination of SiP and SiAs.
However, in analogous art, Stephenson discloses, a superlattice contact film between a semiconductor material and a conductive body, having alternately stacked oxygen (oxide) monolayers and silicon-based layers, the contact region being implanted with a dopant including one or more of boron, arsenic, and phosphorus such that the doped superlattice comprises phosphorus-containing silicon (SiP) layers and/or arsenic-containing silicon (SiAs) layers under the broadest reasonable interpretation set forth above ([0013]-[0014], [0040]-[0045], [0048]-[0050], [0057], [0061], [0063]; Figs. 1-3, 5-8).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Kwon, Tang and Stephenson before him/her, to modify the teachings of a semiconductor memory device as taught by the combination of Kwon and Tang and to include the teachings of a superlattice contact film of alternately stacked oxide layers and doped silicon compound layers disposed at the contact interface between the bit line and the overlying doped contact and channel areas, as taught by Stephenson, since Stephenson's superlattice contact film constrains the N-type contact dopants of Kwon's lower doped layers in place during subsequent thermal processing steps, acts as a dopant diffusion barrier maintaining a shallow and abrupt contact junction, and is compatible with the metal silicide ohmic contact formation employed by Kwon, thereby reducing contact resistance and junction leakage of the bit line contact with predictable results. Absent this important teaching in Kwon, a person with ordinary skill in the art would be motivated to reach out to Stephenson while forming the bit line contact of the semiconductor memory device of Kwon.
Regarding claim 19, the combination of Kwon, Yoo and Stephenson discloses, the semiconductor memory device of claim 18, wherein a thickness of the superlattice layer in the third direction is in a range of about 1 nm to about 100 nm (Stephenson Ref: the superlattice is formed of stacked groups of atomic monolayers, each group being, e.g., three to five silicon monolayers together with an oxygen monolayer, with a semiconductor cap layer of between 2 to 100 monolayers, such that the overall superlattice film is of nanometer-scale thickness within the claimed range (average thickness of a monolayer is typically in the 0.3–1.7 nm range); [0040]-[0041], [0046]-[0047], [0049]). Moreover, the thickness of the superlattice contact film is a result-effective variable directly affecting the dopant-blocking capability and the contact resistance of the contact structure ([0057]-[0063]), and it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to arrive at the claimed thickness range through routine experimentation and optimization, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art (MPEP 2144.05(II)).
Allowable Subject Matter
Claims 3, 5, 11, 16 and 20 are objected to as being dependent upon rejected base claims, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims; with respect to claim 3, the claim would additionally need to be amended to overcome the rejection under 35 U.S.C. 112(b) set forth in this Office action.
Regarding claim 3, the closest prior art, US 2019/0280090 A1 (Stephenson), in conjunction with US 2023/0247821 A1 (Kwon), US 2020/0295008 A1 (Tang) and US 2022/0216239 A1 (Yoo), and in combination with the other claimed features, fails to disclose, “wherein the first compound layer comprises silicon phosphide (SiP), and the second compound layer comprises silicon arsenide (SiAs)”, in combination with the additionally claimed features, as are claimed by the Applicant. While Stephenson discloses that a superlattice contact film may include a dopant comprising at least one of boron, arsenic, and phosphorus, none of the references of record teaches or suggests a first superlattice layer whose compound layers comprise silicon phosphide (SiP) together with a second superlattice layer, on the first superlattice layer, whose compound layers comprise silicon arsenide (SiAs), between a bit line and the channel areas of a vertical-channel memory device.
Specifically, the aforementioned ‘wherein the first compound layer comprises silicon phosphide (SiP), and the second compound layer comprises silicon arsenide (SiAs)’, is material to the inventive concept of the application at hand to provide a stacked, two-composition superlattice direct contact in which the SiAs-containing second superlattice layer can serve as an etch-stop and direct contact plug during backside exposure of the superlattice and formation of the conductive line after capacitor formation, thereby reducing process cost and preventing deterioration of the capacitor by high-temperature processing.
Regarding claim 5, the closest prior art, US 2019/0280090 A1 (Stephenson), in conjunction with US 2023/0247821 A1 (Kwon), US 2020/0295008 A1 (Tang) and US 2022/0216239 A1 (Yoo), and in combination with the other claimed features, fails to disclose, “the semiconductor memory device of claim 1, wherein a concentration of oxygen (O) atoms included in the first oxide layer and the second oxide layer is in a range of about 10¹⁷/cm³ to about 10²²/cm³”, in combination with the additionally claimed features, as are claimed by the Applicant.
Specifically, the aforementioned ‘the semiconductor memory device of claim 1, wherein a concentration of oxygen (O) atoms included in the first oxide layer and the second oxide layer is in a range of about 10¹⁷/cm³ to about 10²²/cm³’, is material to the inventive concept of the application at hand in which the superlattice layer serves as a direct contact plug on which the vertical channel areas, the gate dielectric films, and the back-gate dielectric films land, enabling the vertical channel transistor array to be completed on the superlattice contact before the conductive line is formed from the backside.
Regarding claim 11, the closest prior art, US 2023/0247821 A1 (Kwon), in conjunction with US 2022/0216239 A1 (Yoo), US 2020/0295008 A1 (Tang) and US 2019/0280090 A1 (Stephenson), and in combination with the other claimed features, fails to disclose, “the semiconductor memory device of claim 1, further comprising: a back-gate dielectric film located between the second channel area and the back-gate electrode; and a gate dielectric film located between the second channel area and a first word line that is closer to the second channel area from among the pair of word lines, wherein the back-gate dielectric film and the gate dielectric film are in contact with the superlattice layer”, in combination with the additionally claimed features, as are claimed by the Applicant. In Kwon, the gate dielectric layer (34) and the body line (30) are vertically separated from the bit line (22) by remaining portions of a dielectric line (28R), and none of the references of record teaches or suggests that both a back-gate dielectric film and a gate dielectric film extend to and contact a superlattice layer disposed on the conductive line.
Specifically, the aforementioned ‘the semiconductor memory device of claim 1, further comprising: a back-gate dielectric film located between the second channel area and the back-gate electrode; and a gate dielectric film located between the second channel area and a first word line that is closer to the second channel area from among the pair of word lines, wherein the back-gate dielectric film and the gate dielectric film are in contact with the superlattice layer,’ is material to the inventive concept of the application at hand in which the superlattice layer serves as a direct contact plug on which the vertical channel areas, the gate dielectric films, and the back-gate dielectric films land, enabling the vertical channel transistor array to be completed on the superlattice contact before the conductive line is formed from the backside.
Regarding claim 16, the closest prior art, US 2019/0280090 A1 (Stephenson), in conjunction with US 2023/0247821 A1 (Kwon), US 2020/0295008 A1 (Tang) and US 2022/0216239 A1 (Yoo), and in combination with the other claimed features, fails to disclose, “the semiconductor memory device of claim 12, wherein a concentration of oxygen (O) atoms included in the first oxide layer and the second oxide layer is in a range of about 10¹⁷/cm³ to about 10²²/cm³”, in combination with the additionally claimed features, as are claimed by the Applicant.
Specifically, the aforementioned ‘the semiconductor memory device of claim 12, wherein a concentration of oxygen (O) atoms included in the first oxide layer and the second oxide layer is in a range of about 10¹⁷/cm³ to about 10²²/cm³’, is material to the inventive concept of the application at hand in which the superlattice layer serves as a direct contact plug on which the vertical channel areas, the gate dielectric films, and the back-gate dielectric films land, enabling the vertical channel transistor array to be completed on the superlattice contact before the conductive line is formed from the backside.
Regarding claim 20, the closest prior art, US 2019/0280090 A1 (Stephenson), in conjunction with US 2023/0247821 A1 (Kwon), US 2020/0295008 A1 (Tang) and US 2022/0216239 A1 (Yoo), and in combination with the other claimed features, fails to disclose, “the semiconductor memory device of claim 18, wherein a concentration of oxygen atoms included in the first oxide layer and the second oxide layer is in a range of about 10¹⁷/cm³ to about 10²²/cm³”, in combination with the additionally claimed features, as are claimed by the Applicant.
Specifically, the aforementioned ‘the semiconductor memory device of claim 18, wherein a concentration of oxygen atoms included in the first oxide layer and the second oxide layer is in a range of about 10¹⁷/cm³ to about 10²²/cm³’, is material to the inventive concept of the application at hand in which the superlattice layer serves as a direct contact plug on which the vertical channel areas, the gate dielectric films, and the back-gate dielectric films land, enabling the vertical channel transistor array to be completed on the superlattice contact before the conductive line is formed from the backside.
Examiner's Note (Additional Prior Arts)
The examiner included a few prior arts which were not used in the rejection but are relevant to the disclosure.
1. US 2023/0146530 A1 (Lee) - An integrated circuit device in which a DRAM bit line electrode layer is a superlattice alloy including a plurality of molybdenum (Mo) layers and a plurality of tungsten (W) layers alternately disposed on a direct contact.
2. US 2023/0060149 A1 (Zhu) - A 3D DRAM memory device including vertical transistors in which adjacent word lines are laterally separated by air gaps or dielectric wall structures in the bit line direction, and in which bit line contacts are ohmic metal silicide contacts.
3. US 8,295,080 B2 (Aizawa) - A solid-state memory device including a superlattice laminate having plural crystal layers laminated between a lower electrode and an upper electrode.
4. US 2023/0132574 A1 (Zhao) - A memory device including a vertical transistor with a semiconductor body extending through a stack structure of interleaved dielectric layers and conductive layers.
5. US 2023/0017651 A1 (Jang) - A semiconductor structure including discrete vertical semiconductor pillars, a capacitor structure at the top of each pillar, and a gate structure surrounding a middle area of the pillar.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to S M SOHEL IMTIAZ whose telephone number is (408) 918-7566. The examiner can normally be reached on 8AM-5PM, M-F, PST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S M SOHEL IMTIAZ/Primary Patent Examiner
Art Unit 2812
07/14/2026
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