Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are presented for examination.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-18 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jang et al. (US Pub. No. 2023/0086202 A1), hereafter referred to as Jang.
As to claim 1, Jang discloses a semiconductor package (fig 2A; [0013]) comprising:
a first semiconductor chip (fig 2B, 200B) having first connection pads (265) provided on a first surface (top surface) of the first semiconductor chip (200B), and second connection pads (pads 247 on bottom surface of 210 in chip 200B; [0046]) provided on a second surface (bottom surface) of the first semiconductor chip (200B), the second connection pads electrically connected to the first connection pads (247 on bottom surface is connected to 265 on top surface with 235; [0046]); and
at least one second semiconductor chip (200C) provided on the first semiconductor chip (200B) in a vertical direction, the at least one second semiconductor chip (200C) comprising:
a semiconductor substrate (210) having a first width in a first direction,
a device layer (220) provided on a first surface of the semiconductor substrate (210), the device layer (220) comprising one or more circuit structures (225) and having a second width smaller than the first width in the first direction (direction along cross-section shown in fig 2B shows width of 220 less than 210),
first pads (247 of chip 200C) provided on a first surface of the device layer (220) and directly bonded to the second connection pads (265 of chip 200B) of the first semiconductor chip (200B),
second pads (265 on top surface of chip 200C) provided on a second surface of the semiconductor substrate (200C), and
through-silicon vias (230) provided in the semiconductor substrate (210) and configured to electrically connect the first pads (247) and the second pads (265), the through-silicon vias (230) being connected to the one or more circuit structures (225).
As to claim 2, Jang discloses the semiconductor package of claim 1 (paragraphs above),
wherein the first semiconductor chip (fig 2A, bottom chip includes substrate 100) has a third width greater than the first width (width of 100 is greater than 210).
As to claim 3, Jang discloses the semiconductor package of claim 1 (paragraphs above),
wherein the at least one second semiconductor chip (200C) comprises:
a first insulating layer (241; [0047]) provided on the first surface of the device layer (220) and on one or more side surfaces of the first pads (247); and
a second insulating layer (261; [0047]) provided on a second surface of the semiconductor substrate (210) and on one or more side surfaces of the second pads (265).
As to claim 4, Jang discloses the semiconductor package of claim 3 (paragraphs above),
wherein the first insulating layer (241) has a fourth width smaller than the second width (width of 241 is less than the width of 220).
As to claim 5, Jang discloses the semiconductor package of claim 3 (paragraphs above),
wherein a side surface of the semiconductor substrate, a side surface of the device layer, and a surface of the first insulating layer form a recess portion (fig 2B, sides of 210, 220, 247 forming a recess), and
wherein a width of the recess portion increases towards the first semiconductor chip (widths of 210, 220, 247 recess increases towards 200B).
As to claim 6, Jang discloses the semiconductor package of claim 3 (paragraphs above),
wherein a first separation distance from a side surface of the semiconductor substrate to a side surface of the device layer is equal to or smaller than a second separation distance from the side surface of the semiconductor substrate to a side surface of the first insulating layer (fig 2B, sides of 210, 220, 247).
As to claim 7, Jang discloses the semiconductor package of claim 1 (paragraphs above),
wherein a first separation distance from a side surface of the semiconductor substrate to a side surface of the device layer is proportional to a difference between a coefficient of thermal expansion of the semiconductor substrate and a coefficient of thermal expansion of the device layer (it is inherent that there is a proportion for the distance from the side surfaces and the CTE of structures 210 and 220).
As to claim 8, Jang discloses the semiconductor package of claim 7 (paragraphs above),
wherein the coefficient of thermal expansion of the semiconductor substrate is based on a ratio of a metallic material of the semiconductor substrate, and the coefficient of thermal expansion of the device layer is based on a ratio of a metallic material of the device layer (this statement recited in the claim is true, the CTE is based on the ratios of the materials of the structure, this is an inherent characteristic that is true for the Applicant’s invention and the Jang reference).
As to claim 9, Jang discloses the semiconductor package of claim 1 (paragraphs above),
wherein the semiconductor package further comprises: a molding portion (300; [0044]) surrounding the at least one second semiconductor chip (200B).
As to claim 10, Jang discloses the semiconductor package of claim 9 (paragraphs above),
wherein the molding portion (300) is provided in a recess portion formed by a side surface of the semiconductor substrate and a side surface of the device layer (recess formed by 210 and 220).
As to claim 11, Jang discloses a semiconductor package (fig 2A; [0013]) comprising:
a first semiconductor chip (200B) having first connection pads (265) provided on a first surface of the first semiconductor chip (200B), and second connection pads (247) provided on a second surface of the first semiconductor chip (200B), the second connection pads electrically connected to the first connection pads (pads 265 and 247 are connected by TSV 230); and
a plurality of second semiconductor chips (200C and 200D) provided on the first semiconductor chip (200B) in a vertical direction, each of the plurality of second semiconductor chips (200C/200D) comprising:
a semiconductor substrate (210) having a first width in a first direction (width in cross-sectional view of 2B),
a device layer (220) provided on a first surface of the semiconductor substrate (210), the device layer (220) comprising one or more circuit structures (225) and having a second width smaller than the first width in the first direction (width of 220 is less than 210 in the cross-section shown in fig 2B),
first pads (247) provided on a first surface of the device layer (220),
second pads (265) provided on a second surface of the semiconductor substrate (210), and
through-silicon vias (230) provided in the semiconductor substrate (210) and configured to electrically connect the first pads (247) and the second pads (265), the through-silicon vias (230) being connected to the one or more circuit structures (225),
wherein the first pads (247) of a lowermost second semiconductor chip (200C), among the plurality of second semiconductor chips (200C/D), are directly bonded to the second connection pads (265 of 200B), and the second pads of the plurality of second semiconductor chips are directly bonded to the first pads of an adjacent second semiconductor chip (265 of 200C is directly connected to 247 of 200D), among the plurality of second semiconductor chips (200C/D), and
wherein a recess portion is formed in a side surface of the semiconductor substrate and a side surface of the device layer (recess formed at side surface of 210 and 220).
As to claim 12, Jang discloses the semiconductor package of claim 11 (paragraphs above),
wherein the first semiconductor chip (fig 2A, bottom chip includes substrate 100) has a third width greater than the first width (width of 100 is greater than 210).
As to claim 13, Jang discloses the semiconductor package of claim 11 (paragraphs above),
a molding portion (300) provided on the first semiconductor chip (200B) and the plurality of second semiconductor chips (200C/D), and filling the recess portion (300 fills the recess at 220).
As to claim 14, Jang discloses the semiconductor package of claim 11 (paragraphs above),
wherein each of the plurality of second semiconductor chips (200C/D) comprises:
a first insulating layer (241) provided on the first surface of the device layer (220), and a side surface of the first pads (247); and
a second insulating layer (261) provided on a second surface of the semiconductor substrate (210), and a side surface of the second pads (265).
As to claim 15, Jang discloses the semiconductor package of claim 14 (paragraphs above),
wherein the first insulating layer (241) and the second insulating layer (265) have a fourth width smaller than the first width (width smaller than that of 210).
As to claim 16, Jang discloses the semiconductor package of claim 15 (paragraphs above),
wherein a first separation distance from a side surface of the semiconductor substrate to a side surface of the device layer is proportional to a difference between a coefficient of thermal expansion of the semiconductor substrate and a coefficient of thermal expansion of the device layer (it is inherent that there is a proportion for the distance from the side surfaces and the CTE of structures 210 and 220).
As to claim 17, Jang discloses the semiconductor package of claim 14 (paragraphs above),
wherein a width of the first insulating layer is smaller than the second width of the device layer (width of 241 is less than 220), and a width of the second insulating layer is larger than the width of the first insulating layer (width of 261 is larger than 241).
As to claim 18, Jang discloses the semiconductor package of claim 14 (paragraphs above),
wherein a width of the second insulating layer is smaller than a second width of the device layer (width of 241 is smaller than 220), and a width of the first insulating layer is larger than a width of the second insulating layer (width of 241 at the recess portion of 210 is less than the width of 261 from pad 265 to the mold layer 300).
As to claim 20, Jang discloses a semiconductor package (fig 2A, [0013]) comprising:
a first semiconductor chip (figs 2A-B, 200B including 100) having first connection pads (265) provided on a first surface of the first semiconductor chip (200B), and second connection pads (247) provided on a second surface of the first semiconductor chip, the second connection pads electrically connected to the first connection pads (connected through 230); and
a plurality of second semiconductor chips (200C, 200D) provided on the first semiconductor chip (200B) in a vertical direction, each of the plurality of second semiconductor chips (200C/D) comprising:
a semiconductor substrate (210) having a first area smaller than a second area of the first semiconductor chip (area of 100),
a device layer (220) provided on a first surface of the semiconductor substrate (210), the device layer (220) comprising one or more circuit structures (225) and having a third area smaller than the first area (225 smaller area than 100),
first pads (247) provided on a second surface of the semiconductor substrate (210),
second pads (261) provided on a second surface of the semiconductor substrate (210), and
through-silicon vias (230) provided in the semiconductor substrate (210) and configured to electrically connecting the first pads (247) and the second pads (265), the through-silicon vias (230) being connected to the one or more circuit structures (225),
wherein the first pads of a lowermost second semiconductor chip (247 of 200C), among the plurality of second semiconductor chips, are directly bonded to the second connection pads (265 of 200B), and the second pads of the plurality of second semiconductor chips are directly bonded to the first pads of an adjacent second semiconductor chip (265 of 200C directly bonded to 247 of 200D), among the plurality of second semiconductor chips, and
wherein an edge region of the semiconductor substrate protrudes outside a side surface of the device layer (edge of 210 protrudes outside 220).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang in view of Gong et al. (US Pub. No. 2024/0421013 A1), hereafter referred to as Gong.
As to claim 19, Jang discloses the semiconductor package of claim 14 (paragraphs above).
Jang does not disclose wherein the semiconductor substrate comprises:
a first step region recessed inwardly from the first surface of the semiconductor substrate along a side surface of the device layer; and
a second step region recessed inwardly from the second surface of the semiconductor substrate along a side surface of the second insulating layer.
Nonetheless, Gong discloses a similar bonding structure for stacking semiconductor chips (fig 6B) wherein a semiconductor substrate comprising: a first step region (116A) recessed inwards from a first surface of the semiconductor substrate along a side surface (fig 6B); and
a second step region (116B) recessed inwardly from the second surface of the semiconductor substrate along a side surface (fig 6B).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include the steps of Gong in the package of Jang since this will allow for the molding compound to flow into and fill the recesses created by the steps such that the substrate is secured to the device and stress concentrations at the bonded interface are mitigated.
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub. No. 2020/0135636A1; US Patent No. 11,056,432 B2.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAUN M CAMPBELL whose telephone number is (571)270-3830. The examiner can normally be reached on MWFS: 7:30-6pm Thurs 1-2pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Purvis, Sue can be reached at (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAUN M CAMPBELL/Primary Examiner, Art Unit 2893 7/14/2026
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