DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Claims 1-9 are pending in this Application.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-5, 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Fukuzaki et al (US20160079267A1) in view of Okina et al (US 20200258816 A1).
Re claim 1 Fukuzaki teach a method of manufacturing a semiconductor memory device (fig 1-2), the method comprising:
forming a source select gate layer (SL1, Sl2, fig 2) [0042] over a sacrificial substrate (10, fig. 2).
forming a first source channel (Bottom of 30) penetrating the source select gate layer (SL1, SL2, fig 2) [0042], the first source channel (Bottom 30, fig 2) [0042] being in contact with the sacrificial substrate (10, fig 2B);
forming a preliminary connection structure (SLm, fig 2) [0043-44] connected to the first source channel (Bottom 30);
forming a cell stack structure (CL, fig 1) including a first vertical channel (20) [0024] and conductive patterns (WL, fig 2), wherein the first vertical channel (20) is in contact with the preliminary connection structure (SLm, fig 2) and extends in a first direction (horizontal), and wherein the conductive patterns (WL, fig 2) surround the first vertical channel (20) and are stacked to be spaced apart from each other (see fig 2) in the first direction (horizontal);
forming a bit line (BL, fig 1) connected to the first vertical channel (20 through CL, fig 2);
forming a source slit insulating layer (ST, fig 2) [0065], penetrating the source select gate layer (SL1. SL2, fig 2) [0042] and the preliminary connection structure (SLm, fig 2) [0043-44].
Fukuzaki does not teach forming a first bonding structure over the bit line;
forming a peripheral circuit layer including a peripheral circuit and a second bonding structure overlapping with the peripheral circuit;
bonding the first bonding structure and the second bonding structure to each other; and
forming the source slit insulating layer overlaps with the peripheral circuit layer.
forming the source slit insulating layer overlaps with the peripheral circuit layer
Okina teaches forming a first bonding structure (168, fig 14) [0110] over the bit line (98. Fig 14) [0108];
forming a peripheral circuit layer (700, fig 16) [0111] including a peripheral circuit (708. Fig 16) [0111] and a second bonding structure (788, fig 16) overlapping with the peripheral circuit (708, fig 16) [0111];
bonding the first bonding structure (168, fig 16) [0110] and the second bonding structure (788, fig 16) [0113] to each other; and
removing the sacrificial substrate (10, fig 18) [0119] to expose the first source channel (top of 20, fig 18) [0089].
forming the source slit insulating layer (8P, fig 17) [0106] overlaps with the peripheral circuit layer (708, fig 17) [0106].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Okina into the structure of Fukuzaki to include forming a first bonding structure over the bit line;
forming a peripheral circuit layer including a peripheral circuit and a second bonding structure overlapping with the peripheral circuit;
bonding the first bonding structure and the second bonding structure to each other; and
forming the source slit insulating layer overlaps with the peripheral circuit layer as claimed.
The ordinary artisan would have been motivated to modify Fukuzak based on the teaching of Okina in the above manner, doing so would increase erasing flexibility [0253].
Re claim 3 Fukushima in view of Okina teaches the method of claim 1, wherein forming the first source channel includes: forming a channel hole (MH, fig 5B) [Fukushima, 0024] exposing the sacrificial substrate (10 through 41, fig 5B) the channel hole (MH. Fig 5B) [0024] penetrating the source select gate layer (SL1/SL2, fig 5B) [Fukushima, 0024];
forming a gate insulating layer (gate insulating, fig 5C) [0038] on a sidewall of the source select gate layer (between SGS and 20,fig 5C) [Fukushima, 0038], which is exposed through the channel hole (MH, fig 5C) [Fukushima, 0038];
forming a source channel layer (bottom of 30, fig 2B) along a surface of the channel hole (MH, fig 5D), wherein the source channel layer (bottom of 30) is in contact with the sacrificial substrate (10, fig 5D) and is spaced apart from the source select gate layer (SL1, fig 2B) [Fukushima, 0038] by the gate insulating layer (gate insulating layer , fig 5C) [Fukushima, 0038]; and
filling a central region (central part of MH, fig 5C) of the channel hole (MH), which is opened by the source channel layer (SL1/Sl2, fig 5B), with a source core insulating layer (34, fig 3) and a doped semiconductor pattern (61/62, fig 5C) [Fukushima, 0044].
Re claim 4 Fukushima in view of Okina teach the method of claim 1,
forming the cell stack structure includes: forming a first stack structure (bottom of S41, SL1, fig 2) [Fukushima, 0061] extending to cover the first source channel (SL1/SL2) [0042];
forming a second stack structure (40/43/WL, fig 2) [Fukushima, 0016] by alternately stacking first material layers (40, fig 2) [Fukushima, 0016] and second material layers (WL, fig 2) over the first stack structure (42/41, fig 2);
forming a channel hole (MH, fig 5B) [0024] penetrating the second stack structure (40/ WL), the channel hole (MH, fig 5B) extending into the first stack structure (42/41, fig 2);
forming a memory layer (30, fig 5C) [0026] on a surface of the channel hole (MH, fig 5C);
forming the first vertical channel filling (31/32/35, fig 3) [0026] the channel hole (MH, fig 5C);
forming a slit (ST, fig 5D) [Fukushima 0075] penetrating the second stack structure (40/WL); and
replacing the second material layers (WL, Fig 5D) of the second stack structure(40/WL) with the conductive patterns (word line stacked film) [0016] through the slit (ST) [Fukushima, 0016].
Re claim 5 Fukushima in view of Okina teaches the method of claim 1, wherein forming the preliminary connection structure (SLm, fig 2) [0042] includes: forming a first stack structure (41/SL1/55, fig 4C) [0060] including a first conductive layer (41, fig 4B) [0059] covering the first source channel (bottom of 30, fig 5C) and a sacrificial layer (55, fig 5C) [0060] disposed over the first conductive layer (SL1, fig 5C) [0045];
forming a second stack structure (SL2/WL/40/43, fig 5C) [0066] over the first stack structure (41/SL1/55, fig 4C) [0060];
forming a channel hole (MH, fig 5B) [0024] penetrating the second stack structure (SL2/WL/40/43, fig 5C) [0066], the channel hole extending into the first conductive layer (SL1, fig 5C) of the first stack structure (41/SL1/55, fig 4C) [0060];
forming a memory layer (30, fig 5C), fig 3) on a surface of the channel hole (MH, fig 5B) [0024];
forming the first vertical channel filling (31/32/35, fig 3) [0026] the channel hole (MH, fig 5B) [0024];
forming a slit (ST, fig 5D) [Fukushima 0075] penetrating the second stack structure (40/WL), the slit exposing the sacrificial layer (55, fig 5D) [0055];
forming a sidewall protective layer (43, fig 6C) [0062] on a sidewall of the slit (ST);
forming an opening exposing (55h see fig 6B) [0067] a sidewall of the first vertical channel (31/32/35, fig 3) [0026] by removing a portion of the memory layer (30, fig 6A-6B) [0066-0068] and the sacrificial layer (55, fig 6A-6B) through the slit [0066] ; and
filling the opening with a channel contact layer (34, fig 6B) .
forming a slit (ST, fig 5D) [Fukushima 0075] penetrating the second stack structure (40/WL); and
replacing the second material layers (WL, Fig 5D) of the second stack structure(40/WL) with the conductive patterns (word line stacked film) [0016] through the slit (ST) [Fukushima, 0016].
Re claim 7 Fukushima in view of Okina teach the method of claim 1, wherein a second source channel (61, fig 2) [0044] in contact with the sacrificial substrate (10, fig 2) [Fukushima 0045] is formed, while the first source channel (right bottom 30 fig 2) [Fukushima 0015] is formed,
wherein the cell stack structure (left/right CL, fig 2) [Fukushima 0021] further includes a second vertical channel (right (31/32/35, fig 3) [0026] in contact with the preliminary connection structure (SLm, fig 2) [0043-44]), the second vertical channel (right (31/32/35, fig 3) [Fukushima 0026] extending in parallel to the first vertical channel (left (31/32/35, fig 3) [Fukushima 0026], wherein the source select gate layer (SL1, fig 2) is isolated into a first source select line surrounding the first source channel (right bottom 30, fig 2) and a second source select line (SL2, fig 2) [Fukushima, 0026] surrounding the second source channel (left bottom 30) by the source slit insulating layer (ST, fig 2), and
wherein the preliminary connection structure (SLm, fig 2) is isolated into a first connection pattern (right SLm, fig 2) between the first source channel (right bottom 30) and the first vertical channel (left (31/32/35, fig 3) [Fukushima, 0026] and a second connection pattern (left SLm) between the second source channel (left bottom 30) and the second vertical channel (left (31/32/35, fig 3) [0026] by the source slit insulating layer (ST, fig 2) [Fukushima, 0026]
Re claim 8 Fukushima and Okina teach the method of claim 7, further comprising forming a source layer (18, fig 21) [Okina 0122] connected to the first source channel (left top 20, fig 21) and the second source channel (right top 20, fig 21) [Okina 0122],
wherein the source layer (18, fig 21) [Okina 0122] extends to overlap with the bit line (98, fig 21) [0108] with the first source channel (left top 21) and the second source channel (right top 20), which are interposed between the source layer (18, fig 21) and the bit line (98, fig 21) [Okina 0108].
Re claim 9 Fukushima and Okina teach the method of claim 7, further comprising forming a drain slit insulating layer (72, fig 13A) [Okina 0069] between the first vertical channel (left 58) [0089] and the second vertical channel (right 58), the drain slit insulating layer (72. Fig 13A) penetrating at least one conductive pattern (left 46, fig 13A) among the conductive patterns (left 46 tight 46, fig 13A) [0145], the drain slit insulating layer (72, fig 13A) isolating the at least one conductive pattern (left 46, fig 13A) [Okina 0089] into a first drain select line (top first 46, fig 13A) and a second drain select line (top second 46, fig 13A) [Okina 0132].
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Fukushima as modified by Okina as applied to claim 1 and further in view of Lee et al (US20170338241A1).
Re claim 2 Fukushima in view of Okina teaches the method of claim 1,
Fukushima and Okina do not teach stacking an etch stop layer and a first insulating layer over the sacrificial substrate, before the source select gate layer is formed;
forming a second insulating layer over the source select gate layer; and
removing the etch stop layer, after the source slit insulating layer is formed, wherein the first source channel penetrates the second insulating layer, the first insulating layer, and the etch stop layer.
Lee teaches stacking an etch stop layer (149P, fig 6B) [0067] and a first insulating layer (151, fig.6B) [0085] over the sacrificial substrate (101, shown fig 2), before the source select gate layer (SR1, fig 6B) [0051] is formed;
forming a second insulating layer (153, fig 6B) [0063] over the source select gate layer (SR1, fig 6B; and
removing the etch stop layer (149P, fig 6C) [0067], after the source slit insulating layer (161, fig 6D) [0009] is formed, wherein the first source channel (167, fig 6D) [0110] penetrates the second insulating layer (153, fig 6D), the first insulating layer (151, fig 6D), and the etch stop layer (149P, fig 6C).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Lee into the structure of Fukushima and Okina to include stacking an etch stop layer and a first insulating layer over the sacrificial substrate, before the source select gate layer is formed;
forming a second insulating layer over the source select gate layer; and
removing the etch stop layer, after the source slit insulating layer is formed, wherein the first source channel penetrates the second insulating layer, the first insulating layer, and the etch stop layer as claimed.
The ordinary artisan would have been motivated to modify Fukushima and Okina based on the teaching of Lee in the above manner in order to minimize the size of the semiconductor device [0032].
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Fukushima modified by Okina as applied to claims 1 and 5 above further in view of Seol et al (US20150311301A1)
Re claim 6 Fukushima in view of Okina teaches the method of claim 5, wherein the first stack structure (41/SL1/55, fig 4C) [0060] further includes a first protective layer (bottom 50, fig 3) [0028] disposed between the first conductive layer (SL1, fig 2) and the sacrificial layer (55, fig 2) [0060], a second protective layer (top 50, fig 3) disposed over the sacrificial layer (55, fig, 2), and a second conductive layer (SL2, fig 2) disposed over the second protective layer (top 50),and
wherein the channel contact layer (34, fig 2) is in contact with the first conductive layer (SL1, fig 2) and the second conductive layer (SL2, fig 2).
Fukushima and Okina do not teach the first protective layer and the second protective layer are removed, while the opening is formed.
Seol teaches the first protective layer (left PS, fig 78-79) [0172] and the second protective layer (right PS, fig 78-79) [0172] are removed, while the opening (0105) [0076] is formed.
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Joe into the structure of Fukushima and Okina to include the first protective layer and the second protective layer are removed, while the opening is formed as claimed.
The ordinary artisan would have been motivated to modify Fukushima and Okina based on the teaching of Joe in the above manner for the purpose of improving structural stability of the vertical pattern [0164].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Yu et al (US10825826B2) Three-dimensional memory device having bonding structures connected to bit lines and methods of making the same.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRATIKSHA J LOHAKARE whose telephone number is (571)270-1920. The examiner can normally be reached Monday - Friday 7.30 am-4.30 pm.
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/PRATIKSHA JAYANT LOHAKARE/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 10/7/26
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