DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
2. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
3. Claim(s) 9-20, is/are rejected under 35 U.S.C. 103 as being unpatentable over Chae et al., US-20170301690-A1, and further in view of ZHOU, US-20200251381-A1.
Claims 9, 20. Chae et al., disclose an integrated circuitry (such as the one in fig. 9) comprising:
-a three-dimensional (3D) array region comprising tiers of electronic components (item MR, fig. 9) and a stair-step region, the 3D array region comprising vertically-alternating insulative tiers (item 110) and conductive tiers (item WL, fig. 9) that extend into the stair-step region;
-the stair-step region comprising at least one higher first tread that is immediately-laterally-adjacent a lower second tread along a direction in a vertical cross-section, and a first flight of stairs extending vertically into the first tread along the direction and a second flight of stairs extending vertically into the second tread along the direction (this limitation would read through the structure of fig. 9, [0055] of Chae et al., wherein is disclosed the strings STR are configured in such a way that the memory cells MC are connected in series in a Z-axis direction perpendicular to an XY plane parallel to the top surface of a semiconductor substrate. Accordingly, the channel of the memory cell transistors MC and the select transistors UST and LST may be formed perpendicular to the XY plane).
Chae et al., appear to not clearly specify the limitation of “one of the first flight of stairs and the second flight of stairs having positive slope and the other having negative slope”.
However, in a similar three-dimensional structure, in view of [0032] of ZHOU wherein is disclosed a staircase structure refers to a set of surfaces that include at least two horizontal surfaces (e.g., along x-y plane) and at least two (e.g., first and second) vertical surfaces (e.g., along z-axis) such that each horizontal surface is adjoined to a first vertical surface that extends upward from a first edge of the horizontal surface, and is adjoined to a second vertical surface that extends downward from a second edge of the horizontal surface. Each of the horizontal surfaces is referred as a “step” or “staircase” of the staircase structure. In the present disclosure, a horizontal direction can refer to a direction (e.g., the x-axis or the y-axis) parallel with a top surface of the substrate (e.g., the substrate that provides the fabrication platform for formation of structures over it), and a vertical direction can refer to a direction (e.g., the z-axis) perpendicular to the top surface of the structure.
To provide a 3D memory device having stairs with positive slope and negative slope, it would have been obvious to one of ordinary skill in the art at the time of invention to have positive and negative slopes in 3D memory arrays with stairs are used to control stacking direction, reduce interference, stabilize electrical potential, maintain uniformity, and optimize manufacturing and signal performance
Claims 10, 11 and 15-17. The combination of Chae et al., with ZHOU disclose the integrated circuitry of claim 9 wherein each of the first and second treads has a planar uppermost surface (this limitation would read through the structure of fig. 9, [0116] of Chae et al., wherein is disclosed the semiconductor material filling the channel holes may be planarized to expose the top surface of the uppermost first dielectric layer 210).
Claims 12-14. The combination of Chae et al., with ZHOU disclose the integrated circuitry of claim 9 wherein the first tread and the second tread are within a cavity in the vertically alternating insulative tiers and conductive tiers in the stair-step region, immediately-laterally-adjacent of the stairs in the first and second flights of stairs comprising a plurality of the insulative and conductive tiers (this limitation would read through the structure of fig. 9, [0170] of Chae et al., wherein is disclosed in order to form conductive patterns (i.e., gate electrodes) between the vertically-stacked first dielectric layers 110, the second dielectric layers 115 between the first dielectric layers 110 are removed from the line-type stack structure. That is, openings 152 exposing the charge storage layer 122 are formed between the vertically-stacked first dielectric layers 110. If the second dielectric layers 115 are formed of the same material as the sacrificial dielectric layer 134, the sacrificial dielectric layer 134 and the second dielectric layers 115 may be sequentially removed through an isotropic etch process).
Claim 18. The combination of Chae et al., with ZHOU disclose the integrated circuitry of claim 9 wherein, the first tread and the second tread collectively comprise a stair flight, and further comprising: the stair flight comprising an upper landing that is higher than the first tread and a lower landing that is lower than the second tread; an upper flight of stairs extending vertically into the upper landing along the direction; a lower flight of stairs extending vertically into the lower landing along the direction; and one of the upper flight of stairs and the lower flight of stairs having positive slope and the other having negative slope (this limitation would read through [0032] of ZHOU wherein is disclosed a staircase structure refers to a set of surfaces that include at least two horizontal surfaces (e.g., along x-y plane) and at least two (e.g., first and second) vertical surfaces (e.g., along z-axis) such that each horizontal surface is adjoined to a first vertical surface that extends upward from a first edge of the horizontal surface, and is adjoined to a second vertical surface that extends downward from a second edge of the horizontal surface. Each of the horizontal surfaces is referred as a “step” or “staircase” of the staircase structure. In the present disclosure, a horizontal direction can refer to a direction (e.g., the x-axis or the y-axis) parallel with a top surface of the substrate (e.g., the substrate that provides the fabrication platform for formation of structures over it), and a vertical direction can refer to a direction (e.g., the z-axis) perpendicular to the top surface of the structure.
Claim 19. The combination of Chae et al., with ZHOU disclose the integrated circuitry of claim 9 comprising a plurality of the first treads and a plurality of the second treads, the first treads individually alternating with immediately-laterally-adjacent of the second treads along the direction, individual of the first treads comprising said first flight, individual of the second treads comprising said second flight (this limitation would read through [0054] of ZHOU wherein is disclosed forming an alternating layer stack including a plurality of dielectric layer pairs disposed over a substrate; forming a first mask stack over the alternating layer stack; patterning the first mask stack to define a staircase region including a number of N sub-staircase regions over the alternating layer stack; forming a first staircase structure over the staircase region, the first staircase structure having a number of M steps at each of the staircase regions; and forming a second staircase structure on the first staircase structure. Both N and M are greater than 1 and the second staircase structure has a number of 2 * N * M steps at the staircase region. In some embodiments, the method further includes forming a plurality of vertical semiconductor channels in a stack storage region on the substrate, and each of the staircase regions is adjacent to the stack storage region.
Allowable Subject Matter
. Claims 1-9 are allowed.
Reasons for Allowance
5. The following is an examiner's statement of reasons for allowance:
6. Regarding claims 1-9, the prior art failed to disclose or reasonably suggest the stack in the stair-step region comprising a cavity comprising at least one higher first tread that is immediately-laterally-adjacent a lower second tread along a direction in a vertical cross-section; forming contact openings to the first and second treads through insulative material that is in the cavity directly above the first and second treads, multiple of the contact openings being laterally-spaced relative one another along the direction over each of the first and second treads; forming masking material directly above the insulative material and the contact openings; forming at least two openings through the masking material that are laterally-spaced relative one another along the direction, at least two of the masking-material openings being immediately-laterally-adjacent one another and individually exposing one of the contact openings on opposite ends of the first and second treads; and using the masking material in a plurality of alternating etching and lateral-trimming steps that etch into the first and second treads and widen the masking-material openings to form a first flight of stairs extending vertically into the first tread along the direction and a second flight of stairs extending vertically into the second tread along the direction, one of the first flight of stairs and the second flight of stairs having positive slope and the other having negative slope.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILNER JEAN BAPTISTE whose telephone number is (571)270-7394. The examiner can normally be reached M-T 8:00-6:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/W.J/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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