DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
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The information disclosure statement (IDS) submitted on 7/19/2024, 2/10/2025 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
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Claims 1-9 and 11-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-9 and 11-20 of U.S. Patent No. 12,068,327 in view of Kim (US 2019/0386099).
Regarding claim 1, Pat '327 discloses, in claim 1, a semiconductor device comprising: a substrate including a first region, a second region, and a connecting region placed between the first region and the second region; a plurality of first multi-channel active patterns placed in the first region of the substrate; a plurality of second multi-channel active patterns placed in the second region of the substrate; a first connecting fin type pattern which is placed in the connecting region of the substrate and extends from the first region to the second region in a first direction; a field insulating film which is placed on the substrate and covers an upper surface of the first connecting fin type pattern; and, wherein a width of the first connecting fin type pattern in the second direction decreases and then increases as it goes away from the first region (all limitations are the same with the limitations recited in claim 1 of Pat '327).
Pat '327 does not explicitly disclose a first edge gate electrode which is placed along a boundary between the first region and the connecting region on the field insulating film and extends in a second direction perpendicular to the first direction; a second edge gate electrode which is placed along a boundary between the second region and the connecting region on the field insulating film and extends in the second direction.
Kim teaches, in at least figures 1-2 and related text, the device comprising a first edge gate electrode (130 of 120, [42], [57]) which is placed along a boundary between the first region and the connecting region on the field insulating film (105, [51]) and extends in a second direction (y direction, figures) perpendicular to the first direction (x direction, figures); a second edge gate electrode (230 of 220, [42], [57]) which is placed along a boundary between the second region and the connecting region on the field insulating film (105, [51]) and extends in the second direction (y direction, figures), for the purpose of providing a semiconductor device with increased element integration density and improved reliability and performance ([5]).
Pat '327 and Kim are analogous art because they are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '327 with the specified features of Kim because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '327 to have the first edge gate electrode which is placed along a boundary between the first region and the connecting region on the field insulating film and extends in a second direction perpendicular to the first direction; the second edge gate electrode which is placed along a boundary between the second region and the connecting region on the field insulating film and extends in the second direction, as taught by Kim, for the purpose of providing a semiconductor device with increased element integration density and improved reliability and performance ([5], Kim).
Regarding claim 2, Pat '327 discloses the semiconductor device of claim 1 as described above.
Pat '327 further discloses, in claim 2, the first connecting fin type pattern includes a bridge portion, and a first branch portion and a second branch portion protruding from the bridge portion toward the first region, and the first branch portion and the second branch portion are spaced apart from each other in the second direction (all limitations are the same with the limitations recited in claim 2 of Pat '327).
Regarding claim 3, Pat '327 discloses the semiconductor device of claim 2 as described above.
Pat '327 further discloses, in claim 3, the first connecting fin type pattern includes a third branch portion and a fourth branch portion protruding from the bridge portion toward the second region, and the third branch portion and the fourth branch portion are spaced apart from each other in the second direction (all limitations are the same with the limitations recited in claim 3 of Pat '327).
Regarding claim 4, Pat '327 discloses the semiconductor device of claim 2 as described above.
Pat '327 further discloses, in claim 4, the bridge portion extends to the second region (all limitations are the same with the limitations recited in claim 4 of Pat '327).
Regarding claim 5, Pat '327 discloses the semiconductor device of claim 1 as described above.
Pat '327 further discloses, in claim 5, the first connecting fin type pattern is directly connected to two of the first multi-channel active patterns and two of the second multi-channel active patterns (all limitations are the same with the limitations recited in claim 5 of Pat '327).
Regarding claim 6, Pat '327 discloses the semiconductor device of claim 1 as described above.
Pat '327 further discloses, in claim 6, the first connecting fin type pattern is directly connected to one of the first multi-channel active patterns and two of the second multi-channel active patterns (all limitations are the same with the limitations recited in claim 6 of Pat '327).
Regarding claim 7, Pat '327 discloses the semiconductor device of claim 1 as described above.
Pat '327 further discloses, in claim 7, the first connecting fin type pattern is directly connected to one of the first multi-channel active patterns and one of the second multi-channel active patterns (all limitations are the same with the limitations recited in claim 7 of Pat '327).
Regarding claim 8, Pat '327 discloses the semiconductor device of claim 1 as described above.
Pat '327 further discloses, in claim 8, a second connecting fin type pattern placed in the connecting region of the substrate, wherein an upper surface of the second connecting fin type pattern has a half ring shape (all limitations are the same with the limitations recited in claim 8 of Pat '327).
Regarding claim 9, Pat '327 discloses the semiconductor device of claim 1 as described above.
Pat '327 further discloses, in claim 9, a second connecting fin type pattern placed in the connecting region of the substrate, wherein an upper surface of the second connecting fin type pattern has a half ring shape (all limitations are the same with the limitations recited in claim 9 of Pat '327).
Regarding claim 11, Pat '327 discloses the semiconductor device of claim 1 as described above.
Pat '327 further discloses, in claim 11, at least one of the first multi-channel active pattern and the second multi-channel active pattern includes a lower fin type pattern, and a sheet pattern on the lower fin type pattern (all limitations are the same with the limitations recited in claim 11 of Pat '327).
Regarding claim 12, Pat '327 discloses, in claim 12, a semiconductor device comprising: a substrate including a first region, a second region, and a connecting region placed between the first region and the second region; a plurality of first multi-channel active patterns placed in the first region of the substrate; a plurality of second multi-channel active patterns placed in the second region of the substrate; a first connecting fin type pattern which is placed in the connecting region of the substrate and extends from the first region to the second region in a first direction; a field insulating film which is placed on the substrate and covers an upper surface of the first connecting fin type pattern; and, wherein the first connecting fin type pattern includes a bridge portion, and a first branch portion and a second branch portion protruding from the bridge portion toward the first region, and the first branch portion and the second branch portion are spaced apart from each other in the second direction (all limitations are the same with the limitations recited in claim 12 of Pat '327).
Pat '327 does not explicitly disclose a first edge gate electrode which is placed along a boundary between the first region and the connecting region on the field insulating film and extends in a second direction perpendicular to the first direction; a second edge gate electrode which is placed along a boundary between the second region and the connecting region on the field insulating film and extends in the second direction.
Kim teaches, in at least figures 1-2 and related text, the device comprising a first edge gate electrode (130 of 120, [42], [57]) which is placed along a boundary between the first region and the connecting region on the field insulating film (105, [51]) and extends in a second direction (y direction, figures) perpendicular to the first direction (x direction, figures); a second edge gate electrode (230 of 220, [42], [57]) which is placed along a boundary between the second region and the connecting region on the field insulating film (105, [51]) and extends in the second direction (y direction, figures), for the purpose of providing a semiconductor device with increased element integration density and improved reliability and performance ([5]).
Pat '327 and Kim are analogous art because they are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '327 with the specified features of Kim because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '327 to have the first edge gate electrode which is placed along a boundary between the first region and the connecting region on the field insulating film and extends in a second direction perpendicular to the first direction; the second edge gate electrode which is placed along a boundary between the second region and the connecting region on the field insulating film and extends in the second direction, as taught by Kim, for the purpose of providing a semiconductor device with increased element integration density and improved reliability and performance ([5], Kim).
Regarding claim 13, Pat '327 discloses the semiconductor device of claim 12 as described above.
Pat '327 further discloses, in claim 13, the bridge portion extends to the second region, and a width of the bridge portion in the second direction decreases and then increases, as it goes away from the first branch portion and the second branch portion (all limitations are the same with the limitations recited in claim 13 of Pat '327).
Regarding claim 14, Pat '327 discloses the semiconductor device of claim 13 as described above.
Pat '327 further discloses, in claim 14, the bridge portion is directly connected to two or less of the second multi-channel active patterns (all limitations are the same with the limitations recited in claim 14 of Pat '327).
Regarding claim 15, Pat '327 discloses the semiconductor device of claim 12 as described above.
Pat '327 further discloses, in claim 15, the first connecting fin type pattern includes a third branch portion and a fourth branch portion protruding from the bridge portion toward the second region, and the third branch portion and the fourth branch portion are spaced apart from each other in the second direction (all limitations are the same with the limitations recited in claim 15 of Pat '327).
Regarding claim 16, Pat '327 discloses the semiconductor device of claim 15 as described above.
Pat '327 further discloses, in claim 16, one or both of the third branch portion and the fourth branch portion are directly connected to the second multi-channel active patterns (all limitations are the same with the limitations recited in claim 16 of Pat '327).
Regarding claim 17, Pat '327 discloses the semiconductor device of claim 12 as described above.
Pat '327 further discloses, in claim 17, one or both of the first branch portion and the second branch portion are directly connected to the first multi-channel active patterns (all limitations are the same with the limitations recited in claim 17 of Pat '327).
Regarding claim 18, Pat '327 discloses, in claim 18, a semiconductor device comprising: a substrate including a first region, a second region, and a connecting region placed between the first region and the second region; a plurality of first multi-channel active patterns placed in the first region of the substrate; a plurality of second multi-channel active patterns placed in the second region of the substrate; a first connecting fin type pattern which is placed in the connecting region of the substrate and extends from the first region to the second region in a first direction; a second connecting fin type pattern which is placed in the connecting region of the substrate and has a half ring-shaped upper surface; a third connecting fin type pattern which is placed between the first connecting fin type pattern and the second connecting fin type pattern, and extends in the first direction along a profile of an outer side wall of the first connecting fin type pattern; a field insulating film which is placed on the substrate and covers an upper surface of the first connecting fin type pattern, an upper surface of the second connecting fin type pattern, and an upper surface of the third connecting fin type pattern; a first gate electrode which extends in a second direction perpendicular to the first direction, on the first multi-channel active patterns; a second gate electrode which extends in the second direction, on the second multi-channel active patterns; and, wherein a width of the first connecting fin type pattern in the second direction decreases and then increases, as it goes away from the first region (all limitations are the same with the limitations recited in claim 18 of Pat '327).
Pat '327 does not explicitly disclose a first edge gate electrode which is placed along a boundary between the first region and the connecting region on the field insulating film and is spaced apart from the first gate electrode in the first direction; a second edge gate electrode which is placed along a boundary between the second region and the connecting region on the field insulating film and is spaced apart from the second gate electrode in the first direction; a first source/drain pattern placed between the first gate electrode and the first edge gate electrode; a second source/drain pattern placed between the second gate electrode and the second edge gate electrode.
Kim teaches, in at least figures 1-2 and related text, the device comprising a first edge gate electrode (130 of 120, [42], [57]) which is placed along a boundary between the first region and the connecting region on the field insulating film (105, [51]) and is spaced apart from the first gate electrode (330 of 320, [42], [57]) in the first direction (x direction, figures); a second edge gate electrode (230 of 220, [42], [57]) which is placed along a boundary between the second region and the connecting region on the field insulating film (105, [51]) and is spaced apart from the second gate electrode (430 of 420, [42], [57]) in the first direction (x direction, figures); a first source/drain pattern (150, [66]) placed between the first gate electrode (330 of 320, [42], [57]) and the first edge gate electrode (130 of 120, [42], [57]); a second source/drain pattern (250, [66]) placed between the second gate electrode (430 of 420, [42], [57]) and the second edge gate electrode (230 of 220, [42], [57]), for the purpose of providing a semiconductor device with increased element integration density and improved reliability and performance ([5]).
Pat '327 and Kim are analogous art because they are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '327 with the specified features of Kim because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '327 to have the first edge gate electrode which is placed along a boundary between the first region and the connecting region on the field insulating film and is spaced apart from the first gate electrode in the first direction; the second edge gate electrode which is placed along a boundary between the second region and the connecting region on the field insulating film and is spaced apart from the second gate electrode in the first direction; the first source/drain pattern placed between the first gate electrode and the first edge gate electrode; the second source/drain pattern placed between the second gate electrode and the second edge gate electrode, as taught by Kim, for the purpose of providing a semiconductor device with increased element integration density and improved reliability and performance ([5], Kim).
Regarding claim 19, Pat '327 discloses the semiconductor device of claim 18 as described above.
Pat '327 further discloses, in claim 19, the upper surface of the first connecting fin type pattern has a Y shape (all limitations are the same with the limitations recited in claim 19 of Pat '327).
Regarding claim 20, Pat '327 discloses the semiconductor device of claim 18 as described above.
Pat '327 further discloses, in claim 20, the upper surface of the first connecting fin type pattern has an X shape (all limitations are the same with the limitations recited in claim 20 of Pat '327).
Allowable Subject Matter
Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1 and 10 that recite "the first edge gate electrode wraps around an end of the first multi-channel active patterns, and the second edge gate electrode wraps around an end of the second multi-channel active patterns" in combination with other elements of the base claims 1 and 10.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONG-HO KIM whose telephone number is (571)270-0276. The examiner can normally be reached Monday thru Friday; 8:30 AM to 5PM.
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/TONG-HO KIM/Primary Examiner, Art Unit 2811
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