DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment/Restriction
Applicant’s election without traverse of Species II, FIG. 5, and Claims 1-3, 6-14, and 16-20 in the reply filed on August 28, 2026 is acknowledged. Thus, Claims 4-5 and 15 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on August 28, 2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 6-9, 13-14, and 16-19 are rejected under 35 U.S.C. 102(a)(1)(2) as being anticipated by U.S. Patent Application Publication No. 2018/0211979 A1 to Lee et al. (“Lee”). As to claim 1, Lee discloses a display apparatus, comprising: a substrate (50); a planarization layer (105) disposed on the substrate (50) and that includes a plurality of first regions (at 116) and a second region (above 70) outside the plurality of first regions (at 116), wherein a first distance from a top surface of the substrate (50) to a top surface of each of the plurality of first regions (at 116) is greater than a second distance from the top surface of the substrate (50) to a top surface of the second region (above 70); a plurality of pixel electrodes (125) disposed on the plurality of first regions (at 116) of the planarization layer (105); a bank (372) disposed above the plurality of pixel electrodes (125) and that includes a plurality of openings that respectively correspond to the plurality of pixel electrodes (125); first quantum dot layers (340R) located within first openings of the plurality of openings of the bank (372); second quantum dot layers (340G) located within second openings of the plurality of openings of the bank (372); and transmissive layers (340B) located within remaining openings of the plurality of openings of the bank (372) (See Fig. 1, Fig. 7, ¶ 0051, ¶ 0058, ¶ 0062, ¶ 0065, ¶ 0067, ¶ 0068, ¶ 0070, ¶ 0097, ¶ 0098, ¶ 0100, ¶ 0103, ¶ 0121) (Notes: the limitation “region” is defined as an extensive, continuous part of a surface, space, or body by Dictionary.com). As to claim 2, Lee further discloses wherein, when viewed in a plan view, the plurality of pixel electrodes (125) are respectively located within the plurality of first regions (at 116) (See Fig. 7). As to claim 3, Lee discloses further comprising a plurality of thin-film transistors (TFTs) (at 70), wherein, when viewed the plan view, the plurality of pixel electrodes (125) are respectively electrically connected to the plurality of TFTs (at 70) through contact holes located within the plurality of first regions (at 116) (See Fig. 7) (Notes: the holes are occupied by the pixel electrodes). As to claim 6, Lee discloses further comprising a pixel defining layer (110, 130) disposed on the plurality of first regions (at 116) and the second region (above 70) of the planarization layer (105), wherein the pixel defining layer (110, 130) covers edges of the plurality of pixel electrodes (125) and includes penetration portions (between 110) that expose central portions of the plurality of pixel electrodes (125) (See Fig. 7). As to claim 7, Lee further discloses wherein the pixel defining layer (110, 130) includes an additional penetration portion (above 100) that overlaps the bank (372) when viewed in a plan view (See Fig. 7) (Notes: penetrated by 125). As to claim 8, Lee discloses further comprising: an intermediate layer (135) disposed on the plurality of pixel electrodes (125) and that includes an emission layer (135); an opposite electrode (145) disposed on the intermediate layer (135) and that corresponds to the plurality of pixel electrodes (125); and an encapsulation layer (150, 310, 322, 350) disposed on the opposite electrode (145) (See Fig. 7). As to claim 9, Lee further discloses wherein a distance between top and bottom surfaces of the encapsulation layer (150, 310, 322, 350) in the additional penetration portion (above 100) is greater than a distance between each of the plurality of pixel electrodes (125) and a bottom surface of the bank (372) (See Fig. 7). As to claim 13, Lee discloses a method of manufacturing a display apparatus, the method comprising: forming a planarization layer (105) on a substrate (50), wherein the planarization layer (105) includes a plurality of first regions (at 116) and a second region (above 70) outside the plurality of first regions (at 116), wherein a first distance from a top surface of the substrate (50) to a top surface of each of the plurality of first regions (at 116) is greater than a second distance from the top surface of the substrate (50) to a top surface of the second region (above 70); forming a plurality of pixel electrodes (125) on the plurality of first regions (at 116) of the planarization layer (105); forming a bank (372) that includes a plurality of openings that correspond to the plurality of pixel electrodes (125), wherein the bank (372) is disposed above the plurality of pixel electrodes (125); forming first quantum dot layers (340R) within first openings of the plurality of openings of the bank (372); forming second quantum dot layers (340G) within second openings of the plurality of openings in the bank (372); and forming transmissive layers (340B) within remaining openings of the plurality of openings of the bank (372) (See Fig. 1, Fig. 7, ¶ 0051, ¶ 0058, ¶ 0062, ¶ 0065, ¶ 0067, ¶ 0068, ¶ 0070, ¶ 0097, ¶ 0098, ¶ 0100, ¶ 0103, ¶ 0121) (Notes: the limitation “region” is defined as an extensive, continuous part of a surface, space, or body by Dictionary.com). As to claim 14, Lee further discloses wherein forming the plurality of pixel electrodes (125) comprises respectively forming the plurality of pixel electrodes (125) within the plurality of first regions (at 116) (See Fig. 7). As to claim 16, Lee discloses further comprising forming a pixel defining layer (110, 130) on the plurality of first regions (at 116) and the second region (above 70) of the planarization layer (105), wherein the pixel defining layer (110, 130) covers edges of the plurality of pixel electrodes (125) and includes penetration portions (between 110) that expose central portions of the plurality of pixel electrodes (125) (See Fig. 7). As to claim 17, Lee discloses further comprising: forming an intermediate layer (135) on the plurality of pixel electrodes (125), wherein the intermediate layer (135) includes an emission layer (135); forming an opposite electrode (145) on the intermediate layer (135), wherein the opposite electrode (145) corresponds to the plurality of pixel electrodes (125); and forming an encapsulation layer (150, 310, 322, 350) on the opposite electrode (145), wherein the bank (372) is formed on the encapsulation layer (150, 310, 322, 350) (See Fig. 7). As to claim 18, Lee further discloses wherein forming the pixel defining layer (110, 130) further comprises forming an additional penetration portion (above 100) between the plurality of pixel electrodes (125), when viewed in a plan view (See Fig. 7) (Notes: penetrated by 125). As to claim 19, Lee further discloses wherein a distance between top and bottom surfaces of the encapsulation layer (150, 310, 322, 350) in the additional penetration portion (above 100) is greater than a distance between each of the plurality of pixel electrodes (125) and a bottom surface of the bank (372) (See Fig. 7).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 10-12 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2018/0211979 A1 to Lee et al. (“Lee”) as applied to claims 8 and 19 above, and further in view of U.S. Patent Application Publication No. 2018/0076221 A1 to Hanari (“Hanari”). The teaching of Lee has been discussed above. As to claim 10, although Lee does not further disclose wherein a distance between top and bottom surfaces of the encapsulation layer in the additional penetration portion is about 3.5 μm to about 4.0 μm, Hanari does disclose the encapsulation layer (56) includes a laminated structure ranging from 1 μm to 10 μm and 5 μm to 50 μm (See ¶ 0039). In view of the teaching of Hanari, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Lee to have wherein a distance between top and bottom surfaces of the encapsulation layer in the additional penetration portion is about 3.5 μm to about 4.0 μm because the thickness may be adjusted to provide desired sealing capability and dimension (See ¶ 0039). As to claim 11, although Lee does not further disclose wherein a distance between each of the plurality of pixel electrodes and a bottom surface of the bank is about 2.5 μm to about 3.0 μm, Hanari does disclose the encapsulation layer (56) includes a laminated structure ranging from 1 μm to 10 μm and 5 μm to 50 μm (See ¶ 0039). In view of the teaching of Hanari, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Lee to have wherein a distance between each of the plurality of pixel electrodes and a bottom surface of the bank is about 2.5 μm to about 3.0 μm because the thickness may be adjusted to provide desired sealing capability and dimension (See ¶ 0039). As to claim 12, although Lee does not further disclose wherein a distance between a top surface of the pixel defining layer and a bottom surface of the bank is about 2.0 μm to about 2.5 μm, Hanari does disclose the encapsulation layer (56) includes a laminated structure ranging from 1 μm to 10 μm and 5 μm to 50 μm (See ¶ 0039). In view of the teaching of Hanari, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Lee to have wherein a distance between a top surface of the pixel defining layer and a bottom surface of the bank is about 2.0 μm to about 2.5 μm because the thickness may be adjusted to provide desired sealing capability and dimension (See ¶ 0039). As to claim 20, although Lee does not further disclose wherein a distance between the top and bottom surfaces of the encapsulation layer in the additional penetration portion is about 3.5 μm to about 4.0 μm, Hanari does disclose the encapsulation layer (56) includes a laminated structure ranging from 1 μm to 10 μm and 5 μm to 50 μm (See ¶ 0039). In view of the teaching of Hanari, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Lee to have wherein a distance between the top and bottom surfaces of the encapsulation layer in the additional penetration portion is about 3.5 μm to about 4.0 μm because the thickness may be adjusted to provide desired sealing capability and dimension (See ¶ 0039). Further, the applicant also has not established the critical nature of the “a distance between top and bottom surfaces of the encapsulation layer in the additional penetration portion is about 3.5 μm to about 4.0 μm, a distance between each of the plurality of pixel electrodes and a bottom surface of the bank is about 2.5 μm to about 3.0 μm, a distance between a top surface of the pixel defining layer and a bottom surface of the bank is about 2.0 μm to about 2.5 μm”. “The law is replete with cases in which the difference between the claimed invention and the prior art is some range or other variable within the claims….In such a situation, the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range.” In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir.1990). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to have various ranges. It would also have been obvious to one of ordinary skill in the art at the time the invention was made to discover the optimum or workable ranges by routine experimentations to adjust the thicknesses of the sealing layers to obtain desired properties. See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996) (claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID CHEN whose telephone number is (571)270-7438. The examiner can normally be reached M-F 12-6.
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/DAVID CHEN/Primary Examiner, Art Unit 2815
