Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20, filed February 02, 2026, are examined on the merits.
NON-FINAL.
REMARKS
On pages 6-10, Applicant’s argument to overcome the 35 USC 103 rejection in view of AAPA and Gardner is persuasive. The 35 USC 103 rejection as applied to claims 1-3, 5-11, and 13-20 is withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 6, 9, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Applicant Admitted Prior Art (AAPA) in view of Adelman et al. (Adelman hereafter, US 20220197975 A1).
Claim 1, AAPA discloses a compute unit, comprising:
circuitry configured to:
receive an array ([0002], e.g. vectors…data structure can be the input)…; and
process the data values ([0002], e.g. process the data).
However, AAPA does not disclose the array comprising multiple data values, a shared scale for scaling each of the data values, and one or more type selector bits, the one or more type selector bits indicating a datatype of at least one of the data values…based on the shared scale and the one or more type selector bits.
Adelman discloses the array comprising multiple data values, a shared scale for scaling each of the data values, and one or more type selector bits, the one or more type selector bits indicating a datatype of at least one of the data values…based on the shared scale and the one or more type selector bits ([0076], e.g. SIB byte 704 includes a scale field 752, an index field 754, and a base field 756 to be used in the generation of an address. The scale field 752 indicates scaling factor. The index field 754 specifies an index register to use. In some embodiments, the index field 754 is supplemented with an additional bit from a prefix (e.g., prefix 601) to allow for greater addressing. The base field 756 specifies a base register to use. In some embodiments, the base field 756 is supplemented with an additional bit from a prefix (e.g., prefix 601) to allow for greater addressing. In practice, the content of the scale field 752 allows for the scaling of the content of the index field 754 for memory address generation (e.g., for address generation that uses 2.sup.scale* index+base)).
AAPA discloses the entire array represented in a datatype that datatype “enables downstream hardware (e.g., matrix multipliers) to either process the data in the array directly, or to convert the data in the array to a datatype that is compatible with the hardware and then process the data” (page 1). One of ordinary skill in the art at the time prior to the effective filing date of the instant invention would have been motivated by AAPA to improve the prior art. Therefore, it would have been obvious for one of ordinary skill in the art to use AAPA with the array of Adelman. The benefit would be to enables downstream hardware (e.g., matrix multipliers) to either process the data in the array directly, or to convert the data in the array to a datatype that is compatible with the hardware and then process the data.
Claim 6, AAPA as modified discloses wherein the array is part of a machine learning (ML) application, wherein the circuitry comprises matrix multipliers configured to process the data values (AAPA, [0002], e.g. machine learning…vectors, matrices…matrix multipliers).
Claims 9 and 17 are directed to a compute unit and system comprising the same steps as claim 1. Claims 9 and 17 are similarly rejected under the same rationale as claim 1, supra.
Claim(s) 2, 3, 5, 7, 8, 10, 11, 13-16, and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Applicant Admitted Prior Art (AAPA) in view of Adelman et al. (Adelman hereafter, US 20220197975 A1), as applied to claims 1, 6, 9, and 17 above, in further view of Gardner (US 2005/0138051 A1).
Claim 2, AAPA as modified discloses the claimed invention except for the limitation of the one or more type selector bits includes a plurality of type selector bits, wherein a first bit of the plurality of type selector bits indicates a first data value of the multiple data values is a first datatype and a second bit of the plurality of type selector bits indicates a second data value of the multiple data values is a second datatype. Gardner discloses the one or more type selector bits includes a plurality of type selector bits, wherein a first bit of the plurality of type selector bits indicates a first data value of the multiple data values is a first datatype and a second bit of the plurality of type selector bits indicates a second data value of the multiple data values is a second datatype (Gardner, Figures 2C, e.g. DATATYPE, data1, data2, data3).
Gardner discloses a technique that facilitates seamless and easy conversion of various EDI data 12 formats without any need for human intervention or lengthy and cumbersome coding to handle each EDI data-type with a separate section of code (page 2, [0019]). One of ordinary skill in the art at the time prior to the effective filing date of the instant invention would have been motivated by Gardner to improve the prior art. Therefore, it would have been obvious for one of ordinary skill in the art to use AAPA as modified with the array of Gardner. The benefit would be to facilitate seamless and easy conversion of data formats without any need for human intervention.
Claim 3, AAPA as modified discloses wherein the first bit of the plurality of type selector bits indicates at least two of the multiple data values are the first datatype and the second bit of the plurality of type selector bits indicates at least two of the multiple data values are the second datatype (Gardner, Figures 2C, e.g. DATATYPE, data1, data2, data3).
Claim 5, AAPA as modified discloses the one or more type selector bits indicates that each of the data values are a same datatype (Gardner, page 2, [0018], e.g. a PERL character indexed array, of subroutines is pre-built to process each separate data-type by a corresponding subroutine. The disclosure of Gardner suggests each subroutine is for data of the same datatype), wherein the one or more type selector bits have different values for indicating each of the data values are different datatypes (Gardner, page 2, [0018], e.g. a PERL character indexed array, of subroutines is pre-built to process each separate data-type by a corresponding subroutine. The disclosure of Gardner suggests different subroutines correspond to data of each respective datatype).
Claim 7, AAPA as modified discloses the circuitry comprises upcast circuitry is configured to convert the data values in the array from a first datatype to a higher precision datatype using the one or more type selector bits, wherein the matrix multipliers are configured to perform multiplications when the data values are in the higher precision datatype (Gardner, page 2, [0019], e.g. this technique facilitates seamless and easy conversion of various EDI data 12 formats without any need for human intervention or lengthy and cumbersome coding to handle each EDI data-type with a separate section of code, and [0020], e.g. A particular PERL script is selected to convert the received daily EDI data 12 as shown at step 40 depending upon the type of the data as described above. The PERL DBASE::AccessX module at step 42 converts the EDI data 12 processed by the selected PERL script into a database record and stores it in the daily database 20 (see FIG. 1). In a similar manner, weekly EDI data 12 is sourced at step 48, converted by an automatically selected PERL script at step 50, and converted into a weekly database 18 record format at step 54).
Claim 8 recites the array is transmitted from memory to the compute unit when the data values are the first datatype. In regard to the limitation of “when the data values are the first data type”, such limitation has been interpreted as a conditional statement wherein the step of “transmitted” is only performed when the specified condition has been met. Or the step is not performed when said condition has not been met. Therefore, the step of “transmitted…” has been interpreted as being optional. Claim scope is not limited by claim language that suggests or makes optional but does not require steps to be performed. (see MPEP 2111.04 [R-3]).
Claims 10, 11, 13-16, and 18-20, are directed to a compute unit and system comprising the same steps as claim 2, 3, 5, 7, and 8. Claims 10, 11, 13-16, and 18-20 are similarly rejected under the same rationale as claim 2, 3, 5, 7, and 8, supra.
Allowable Subject Matter
Claims 4 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 4 and 12 are free of any prior art because of the limitation of “wherein the at least two of multiple data values corresponding to the first bit comprises data values in at least two rows and at least two columns of the array and the at least two of multiple data values corresponding to the second bit comprises data values in at least two rows and at least two columns of the array.”
CONCLUSION
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Cheyne D Ly/
Primary Examiner, Art Unit 2152