DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on July 17, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Interpretation
It is noted what Applicant means by the term “data protection” by what is stated in paragraph [0005] of the specification. Applicant conveys that data protection is used in the context of ensuring the integrity of data written to and read from memory devices, such as a “chip kill” (also written as “chipkill” in the art) scheme used to improve recovery or correction of data in the event of a physical fail such as a chip fail or a channel fail. Note that this is different from safety or securing or preventing data from inadvertent or unauthorized reading or writing. Examples of prior art references disclosing the background of chipkill are US 6493843 and US 20020013929.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-9, 12-14, and 16 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3, 5, 9, and 12 of U.S. Patent No. US 12,046,322. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reasons:
Regarding claims 1-3: Claim 1 of the reference patent teaches the subject matter of these claims.
Regarding claims 4-5: Claim 3 of the reference patent teaches the subject matter of these claims.
Regarding claims 6-7: Claim 5 of the reference patent teaches the subject matter of these claims.
Regarding claim 8-9: Claim 9 of the reference patent teaches the subject matter of these claims.
Regarding claims 12-14, and 16: Claim 12 of the reference patent teaches the subject matter of these claims.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11 and 18 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 11: There is insufficient antecedent basis for this limitation “the first operation mode” in the claim.
Regarding claim 18: Sine the grammar is not correct in the phrase “wherein a number of the plurality of first channels of the plurality of channels each transfer two first symbols” due to the mismatch between the verb (transfer) and the singular subject (each) then it is not definite whether Applicant meant to say “wherein each one of a number of the plurality of first channels of the plurality of channels transfers two first symbols” or “wherein a number of the plurality of first channels of the plurality of channels together transfer two first symbols”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4-12, 14-16, 18, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Linstadt (US 2015/0254192 A1).
Regarding claim 1: Linstadt (FIG. 2A-B; [0028-0035]) teaches an apparatus, comprising:
a memory comprising a plurality of memory devices (120-1,120-2 or 202-1, 202-2); and
a memory controller (110) coupled to the memory via a plurality of channels comprising respective subsets of the plurality of memory devices, the memory controller comprising data protection circuitry ([0042]; circuitry in the controller that confirms that the memory devices have correct connectivity configuration; “memory controller 110 may repeat the discovery process or issue an error signal indicating that discovery cannot be completed”, hence the controller ensures the integrity of data written to and read from the memory devices) configured to:
accommodate a first codeword configuration of a number of codewords (in x4 or 4-bit data bus width mode, a 4-bit codeword is seen input to or output from controller 110 in FIG. 2A at one time for each channel or one 8-bit codeword is input to or output from controller 110 at one time; [0028-0032]);
accommodate a second codeword configuration of the number of codewords (in x2 or 2-bit data bus width mode, a 2-bit codeword is seen input to or output from controller 110 in FIG. 2A at one time for each channel or one 4-bit codeword is input to or output from controller 110 at one time; [0033-0035]); and
switch (by using logic 208 and the multiplexers 204; [0037]) between a first operating mode of the plurality of memory devices and a second operating mode of the plurality of memory devices, wherein the first operating mode is associated with the first codeword configuration, and wherein the second operating mode is associated with the second codeword configuration that is different from the first codeword configuration.
Regarding claim 4: Linstadt (FIG. 2A-B) teaches the apparatus of claim 1, wherein data transferred from the plurality of memory devices forms codewords (a codeword having 8 bits or 4 bits as explained above), each codeword including data from a first memory device (120-1) of the plurality of memory devices and data from a second memory device (120-2) of the plurality of memory devices.
Regarding claim 5: Linstadt (FIG. 2A-B) teaches the apparatus of claim 4, wherein the first memory device (120-1 or 202-1) and the second memory device (120-2 or 202-2) are coupled to different channels (each serializer 206 is considered to be coupled to the controller via a respective channel or bus).
Regarding claim 6: Linstadt (FIG. 2A-B) teaches the apparatus of claim 1, wherein encoder circuitry (logic 208 and/or serializer 206) configured to map I/O pins to codewords when the data protection circuitry is in the first operating mode is a same encoder circuitry configured to map I/O pins to codewords when the data protection circuitry is in the second operating mode ([0031-0032]).
Regarding claim 7: Linstadt (FIG. 2A-B) teaches the apparatus of claim 1, wherein decoder circuitry (logic 208 and/or serializer 206) configured to map I/O pins to codewords when the data protection circuitry is in the first operating mode is a same decoder circuitry configured to map I/O pins to codewords when the data protection circuitry is in the second operating mode ([0031-0032]).
Regarding claim 8: Linstadt (FIG. 2A-B; [0028-0035]) teaches a method, comprising:
receiving, by a controller, data corresponding to a number of codewords (a 4-bit codeword is seen input to or output from controller 110 in FIG. 2A at one time for each channel when in x4 mode and a 2-bit codeword is seen input to or output from controller 110 in FIG. 2B at one time for each channel when in X2 mode) from a plurality of memory channels (two channels), wherein each memory channel is coupled to a number of memory devices (memories 120-1 and 120-2), and wherein each memory device of the number of memory devices:
is configured to store data corresponding to one or more of the number of codewords (each memory core corresponds to a respective codeword that can have any one of two configurations corresponding to the mode); and
has a particular operating mode (x4 or x2) corresponding to its input/output (I/O) width; and
operating data protection circuitry ([0042]; circuitry in the controller that confirms that the memory devices have correct connectivity configuration; “memory controller 110 may repeat the discovery process or issue an error signal indicating that discovery cannot be completed”, hence the controller ensures the integrity of data written to and read from the memory devices) of the controller configured to:
accommodate a first codeword configuration of the number of codewords (in x4 or 4-bit data bus width mode, a 4-bit codeword is seen input to or output from controller 110 in FIG. 2A at one time for each channel; [0028-0032]); and
accommodate a second codeword configuration of the number of codewords (in x2 or 2-bit data bus width mode, a 2-bit codeword is seen input to or output from controller 110 in FIG. 2A at one time for each channel; [0033-0035]) that is different from the first codeword configuration (x4 and x2 are different in bus bit width).
Regarding claim 9: Linstadt (FIG. 2A-B; [0028-0035]) teaches the method of claim 8, wherein each respective memory channel of the plurality of memory channels has a first channel width (4-bits) or a second channel width (2-bits) that is different from the first channel width.
Regarding claim 10: Linstadt (FIG. 2A-B) teaches the method of claim 9, wherein one respective memory device [of the number of memory devices] at a time transfers data through the respective memory channel in response to the respective memory channel having the first channel width (x4 mode, which is a mode of operation using a 4-bit wide bus or channel) and the respective memory device having a first operating mode (the respective memory device is operated in the first mode or configuration).
Regarding claim 11: In so far as definite Linstadt (FIG. 2A-B) teaches the method of claim 9, further comprising transferring, by two respective memory devices [of the number of memory devices] ((memories 120-1 and 120-2) simultaneously, data through the respective memory channel in response to the memory channel having the second channel width (x2 mode, which is a mode of operation using a 2-bit wide bus or channel) and the respective memory device having the first [second] operation mode (the respective memory device is operated in the certain mode or configuration).
Regarding claim 12: Linstadt (FIG. 2A-B; [0028-0035]) teaches an apparatus, comprising:
a memory controller (110) configured to map input/output (I/O) pins to receive codewords (a codeword to/from each respective serializer) from a plurality of memory devices ([0037]);
a plurality of channels coupled to the memory controller and configured to transfer the codewords from the plurality of memory devices to the memory controller (a bus or channel from each serializer to the controller 110 is illustrated in FIG. 2B); and
a plurality of multiplexors (204-1, 204-2) configured to switch between a plurality of signaling paths for the codewords.
Regarding claim 14: Linstadt (FIG. 2A-B) teaches the apparatus of claim 12, wherein each codeword includes a plurality of symbols (bits, such as 4 or 2 depending on the mode).
Regarding claim 15: Linstadt (FIG. 2A-B) teaches the apparatus of claim 14, wherein the plurality of multiplexors are configured to select a respective symbol of a respective codeword based on a mode of a respective memory device (each multiplexer 204 selects bits of a respective codeword based on the mode of the device, the mode being x4 or x2).
Regarding claim 16: Linstadt (FIG. 2A-B) teaches the apparatus of claim 12, wherein a first codeword comprises a plurality of first symbols (a first set of bits) and a second codeword comprises a plurality of second symbols (a second set of bits).
Regarding claim 18: In so far as definite Linstadt (FIG. 2A-B) teaches the apparatus of claim 16, wherein a number of first channels of the plurality of channels (a first channel on the left side in FIG. 2B) each transfer two first symbols to the memory controller to form the first codeword (the first channel transfers 4 bits to form a respective 4-bit codeword in x4 mode) and a number of second channels (a second channel on the right side in FIG. 2B) of the plurality of channels each transfer two second symbols (2 bits) to the memory controller to form the second codeword (the second channel transfers 2 bits to form a respective 2-bit codeword in the x2 mode).
Regarding claim 20: Linstadt (FIG. 2A-B) teaches the apparatus of claim 12, wherein a first amount of data per beat is transferred through a respective channel responsive to the respective channel having a first channel width (4 bits of data from each serializer at one time are input/output in x4 mode, wherein each channel has a data width of 4 bits), and a second amount of data per beat is transferred through the respective channel in response to the respective channel having a second channel width (2 bits of data from each serializer at one time are input/output in x2 mode, wherein each channel has a data width of 2 bits).
Allowable Subject Matter
Claims 17 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 17: The prior art made of record and considered pertinent to the applicant's disclosure does not teach or suggest the claimed limitation of each respective channel simultaneously transfers a first symbol to the memory controller to form the first codeword and transfers a second symbol to the memory controller to form the second codeword in combination with the other limitations thereof as is recited in the claim.
Regarding claim 19: The prior art made of record and considered pertinent to the applicant's disclosure does not teach or suggest the claimed limitation of each respective channel transfers a first symbol to the memory controller to form the first codeword, transfers a second symbol to the memory controller to form the second codeword, transfers a third signal to the memory controller to form a third codeword, and transfers a fourth symbol to the memory controller to form a fourth codeword in combination with the other limitations thereof as is recited in the claim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY W RADKE whose telephone number is (571)270-1622. The examiner can normally be reached M-F 9-6 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JAY W. RADKE
Primary Examiner
Art Unit 2827
/JAY W. RADKE/Primary Examiner, Art Unit 2827