DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
2. Claims 50-52 and 55 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bae et al. U.S. Patent Application Publication 2017/0104152 A1 (the ‘152 reference, of record and matured into U.S. Patent 9,660,186 B2).
The reference discloses in Fig. 2H, para [28] (paragraph(s) [0028]) and other text an integrated circuit device as claimed.
Referring to claim 50, the ‘152 reference discloses an integrated circuit device, comprising:
a substrate (10);
a memory cell disposed over the substrate, the memory cell comprising a bottom electrode (metal seed layer 31), a resistance switching structure (comprising ferromagnet 32/33/34, tunneling insulator 35, and ferromagnet 36), and a top electrode (metal capping/hardmask 38/40), wherein the memory cell has a top side, a bottom side, and an outer surface between the top side and the bottom side, and at least one of the top electrode (38/40) or the bottom electrode (31)comprises a first metal, wherein the first metal is tantalum, titanium, tungsten, or ruthenium;
an oxide (oxidized by-product 52, para [38, 43]) of the first metal on the outer surface and in contact with the resistance switching structure (32/33/34/35/36); and
a sidewall spacer (60, para [38]) around the memory cell, wherein the oxide (52) of the first metal is between the sidewall spacer (60) and the memory cell; and
a bottom electrode via (electrode 25, para [27]) in direct contact with the bottom electrode (31), wherein the bottom electrode (31) is wider than the bottom electrode via (25).
Referring to claim 51, Fig. 2H depicts that the oxide (52) of the first metal forms a layer having a tapering thickness on the outer surface.
Referring to claim 52, the reference further discloses that the sidewall spacer (60) comprises silicon nitride (para [38]).
Referring to claim 55, the reference further discloses a dielectric layer (20, para [27]), wherein the bottom electrode via (25) is disposed in the dielectric layer (20) and the oxide (52) of the first metal is in contact with the dielectric layer (20).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. §103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claim 57 is rejected under 35 U.S.C. §103 as being unpatentable over Bae et al. U.S. Patent Application Publication 2017/0104152 A1 (the ‘152 reference, of record and matured into U.S. Patent 9,660,186 B2 in view of Sonoda U.S. Patent Application Publication 20190280187.
Referring to claim 57, the ‘152 reference discloses a method of manufacturing an integrated circuit (IC) device comprising a semiconductor substrate (10, Fig. 2H, para [27]) and a memory stack, but does not disclose forming a metallization layer over a semiconductor substrate.
Sonoda, in disclosing a method of manufacturing an integrated circuit (IC) device comprising a semiconductor substrate (21, Fig. 3, para [27]) and a memory stack (33/RC/38, para [51-53]) over the semiconductor substrate, teaches forming a metallization layer (metal layer, para [64]) over the semiconductor substrate for the implied purpose of controlling the memory stack.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the reference’s method to include forming a metallization layer over a semiconductor substrate. One would have been motivated to make such a modification in view of the teachings in Sonoda for the implied purpose of controlling the memory stack.
Thus, such a modification would have resulted in a method of manufacturing an integrated circuit (IC) device (Fig. 2H, para [38]), the method comprising:
forming a metallization layer over a semiconductor substrate (10);
depositing a dielectric layer (20, para [27]) over the metallization layer;
forming a bottom electrode via (25, para [27] in the dielectric layer (20);
forming a memory stack over the dielectric layer (20) and the bottom electrode via (25), wherein the memory stack comprises a bottom electrode layer (seed metal layer 31), a resistance switching structure (comprising ferromagnet 32/33/34, tunneling insulator 35, and ferromagnet 36), and a top electrode layer (metal capping/hardmask 38/40) and at least one of the bottom electrode layer(31) or the top electrode layer (38/40) comprises a first metal, wherein the first metal is tantalum, titanium, tungsten, or ruthenium;
patterning the memory stack (para [29]) to form a memory cell comprising the resistance switching structure (32/33/34/35/36), wherein the memory cell (31/32/33/34/35/36/38/40) is wider than the bottom electrode via (25);
oxidizing some of the first metal on a sidewall of the memory cell to form an oxidized electrode metal layer (oxidized by-product 52, para [38, 43]) on the sidewall of the memory cell; and
forming a spacer (60, para [38]) around the memory cell, wherein the spacer comprises silicon nitride, and the oxidized electrode metal layer (52) is between the spacer (60) and the memory cell (31/32/33/34/35/36/38/40).
Allowable Subject Matter
4. Claims 41-49 are allowable over the prior art of record.
Claims 53-54, 56 and 58-60 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for the indication of allowable subject matter: The cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to teach or render obvious an integrated circuit device and a method of manufacturing an integrated circuit (IC) device with all exclusive limitations as recited in claims 41, 53, 56, 58, 59 and 60, which may be characterized (claim 41) in that the first layer has a thickness that tapers toward the top side, (claim 53) in that a second layer is around and above the sidewall spacer, wherein the second layer comprises silicon carbide, silicon carbonitride, silicon oxycarbide, or silicon oxycarbonitiride, (claim 56) metal oxide is disposed underneath the sidewall spacer, wherein the sidewall spacer is in contact with the metal oxide, (claim 58) in etching the oxidized electrode metal layer, and in that after etching the oxidized electrode metal layer is tapered, (claim 59) oxidizing the first metal to form an oxidized electrode metal layer comprises depositing an oxide on the memory cell, and (claim 60) in depositing a second layer over the spacer, and in that the second layer comprises silicon carbide, silicon carbonitride, silicon oxycarbide, or silicon oxycarbonitiride.
Conclusion
5. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TU TU V HO whose telephone number is (571)272-1778. The examiner can normally be reached on Monday to Thursday 6:30 - 15:00, Monday through Thursday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff W Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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08-24-2026
/TU-TU V HO/Primary Examiner, Art Unit 2818
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