Prosecution Insights
Last updated: August 17, 2026
Application No. 18/779,114

TRANSISTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Non-Final OA §102
Filed
Jul 22, 2024
Priority
Apr 15, 2024 — TW 113114033
Examiner
ERDEM, FAZLI
Art Unit
Tech Center
Assignee
Powerchip Semiconductor Manufacturing Corporation
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
4m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
919 granted / 1077 resolved
+25.3% vs TC avg
Strong +16% interview lift
Without
With
+16.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
27 currently pending
Career history
1100
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
50.2%
+10.2% vs TC avg
§102
37.9%
-2.1% vs TC avg
§112
7.5%
-32.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1077 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Maszara et al. (20030178689). Regarding Claim 1, in Figs. 1 and 2 and in paragraphs 0022, 0024, 0033, 0034 and 0040, Maszara et al. discloses a semiconductor structure, comprising: a substrate 18, having an active area 32a/32b wherein the active area has a first side and a second side opposite to each other; a gate 38a/38b/40a/40b, disposed on the substrate in the active area, wherein the gate comprises a body portion 38a/40a, a first extension portion 38b/40b and a second extension portion (left or right), the first extension portion and the second extension portion are connected to the body portion, the body portion extends in a first direction, and the first extension portion is located at the first side and partially overlaps the active area, the second extension portion is located at the second side and partially overlaps the active area, and a material of the first extension portion 38a/40a and the second extension portion 38b/40b different from a material of the body portion; a first doped region and a second doped region, located in the active area, and disposed in the substrate at both sides of the gate in a second direction intersecting the first direction; and a gate dielectric layer, disposed between the gate and the substrate (examiner is in the opinion that one can take portions of 38a/38b and 40a/40b as body and extension portions). Regarding Claim 2, the material of the body portion comprises metal, and the material of the first extension portion and the second extension portion comprises polysilicon (see paragraph 0029, 0033,0040) Regarding Claim 3, the body portion extends across the active area and extends beyond the active area. Regarding Claim 4, wherein the first extension portion and the second extension portion are respectively located at opposite sides of the body portion in the second direction. Regarding Claim 5, wherein the first extension portion and the second extension portion are respectively located at the same side of the body portion in the second direction. Regarding Claim 6, the first extension portion comprises two sub-extension portions, and the two sub-extension portions are respectively located at opposite sides of the body portion in the second direction (again, the examiner is in the opinion gate electrodes 38a/38b/40a/40b can be divided in portions to arrive at sub-extension portions) Regarding Claim 7, the second extension portion comprises two sub-extension portions, and the two sub-extension portions are respectively located at opposite sides of the body portion in the second direction. Regarding Claim 8, the entire body portion is located in the active area, the first extension portion and the second extension portion are respectively located at opposite sides of the body portion in the first direction, and widths of the first extension portion and the second extension portion in the second direction is greater than a width of the body portion in the second direction. Regarding Claim 9, in Figs 1 and 2 and paragraphs 0022, 0024, 0029, 0033, 0034, 0040, elements 38a/38b/40a/40b, manufacturing method of a semiconductor structure, comprising: providing a substrate, wherein the substrate has an active area, and the active area has a first side and a second side opposite to each other; forming a gate on the substrate in the active area, wherein the gate comprises a body portion, a first extension portion and a second extension portion, the first extension portion and the second extension portion are connected to the body portion, the body portion extends in a first direction, and the first extension portion is located at the first side and partially overlaps the active area, the second extension portion is located at the second side and partially overlaps the active area, and a material of the first extension portion and the second extension portion is different from a material of the body portion; forming a gate dielectric layer between the gate and the substrate; and forming a first doped region and a second doped region in the substrate at both sides of the gate in a second direction intersecting the first direction. Regarding Claim 10, the material of the body portion comprises metal, and the material of the first extension portion and the second extension portion comprises polysilicon. Regarding Claim 11, forming method of the gate comprises: forming a gate structure on the substrate, wherein the gate structure is composed of the gate dielectric layer and a first gate material layer located on the gate dielectric layer, the gate structure comprises an initial body portion, a first initial extension portion and a second initial extension portion, the first initial extension portion and the second initial extension portion are connected to the initial body portion, the initial body portion extends in the first direction, the first initial extension portion is located at the first side and partially overlaps the active area, and the second initial extension portion is located at the second side and partially overlaps the active area; removing the first gate material layer in the initial body portion to form a gate groove; and forming a second gate material layer in the gate groove, wherein the second gate material layer constitutes the body portion, the first gate material layer in the first initial extension portion constitutes the first extension portion, and the first gate material layer in the second initial extension portion constitutes the second extension portion. Regarding Claim 12, a material of the first gate material layer comprises polysilicon, and a material of the second gate material layer comprises metal. Regarding Claim 13, the initial body portion extends across the active area and extends beyond the active area. Regarding Claim 14, wherein the first initial extension portion and the second initial extension portion are respectively located at opposite sides of the initial body portion in the second direction. Regarding Claim 15, the first initial extension portion and the initial second extension portion are respectively located at the same side of the initial body portion in the second direction. Regarding Claim 16, wherein the first initial extension portion comprises two initial sub-extension portions, and the two initial sub-extension portions are respectively located at opposite sides of the initial body portion in the second direction. Regarding Claim 17, wherein the second initial extension portion comprises two initial sub-extension portions, and the two initial sub-extension portions are respectively located at opposite sides of the initial body portion in the second direction. Regarding Claim 18, wherein the entire initial body portion is located in the active area, the first initial extension portion and the second initial extension portion are respectively located at opposite sides of the initial body portion in the first direction, and widths of the first initial extension portion and the second initial extension portion in the second direction are greater than a width of the initial body portion in the second direction. Examiner is including non-applied relevant art Yu et al. (20050035404) as asymmetric gate electrode structure. Although all the portions of the gate electrode is made of the same material, Maszara discloses portions of the gate structure of different materials. Further, non-applied relevant art Sandhu 20070145430 discloses asymmetric gate with different material portions. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAZLI ERDEM whose telephone number is (571)272-1914. The examiner can normally be reached M-F, 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FAZLI ERDEM/Primary Examiner, Art Unit 2812 7/11/2026
Read full office action

Prosecution Timeline

Jul 22, 2024
Application Filed
Jul 15, 2026
Non-Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
99%
With Interview (+16.0%)
2y 5m (~4m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1077 resolved cases by this examiner. Grant probability derived from career allowance rate.

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