DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Specie A (Claims 1-10) in the reply filed on 9/14/26 is acknowledged. The traversal is on the ground(s) that the drawings cited in the election of species do not properly label the different inventions. This is not found persuasive because the labeling of the figures of the invention is determined by Applicants, and inventions A and B comprise mutually exclusive limitations; either there is an overlap, or there isn’t one. Moreover, Specie C does not require the different regions of Species A and B, and pertain to limitations which relate to the different positioning and dimensions of the claimed elements. Rejoinder issues will be addressed upon indication of allowable subject matter.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Hong et al (US 2021/0257449) in view of (US 2021/01257449).
With respect to Claim 1, Hong et al disclose a semiconductor device (Figures 1, 3A and 5A-5B) comprising: a substrate having a first region (Figure 1, R1) and a second region (Figure 1, R2) surrounding the first region; an integrated circuit structure (Figures 5A-5B) on the substrate in the first region (Figure 1, R1); a guard ring (Figure 3A, 200) surrounding the integrated circuit structure on the substrate in the second region; a plurality of vias (Figure 3A, 271) arranged on the guard ring (Figure 3A, 200); and a conductive line (Figure 3A, 281) arranged on the plurality of vias (Figure 3A, 271); wherein the integrated circuit structure comprises a circuit active fin (Figures 5A-5B, 105) on the substrate in the first region (Figure 1 and Figures 5A-5B, R1), a gate structure (Figure 5A-5B, 140) intersecting the circuit active fin (Figures 5A-5B, 105), a source/drain region (Figure 5A-5B 130) on an active fin adjacent to a side surface of the gate structure, a circuit contact structure (Figure 5A-5B, 155) on the source/drain region (Figure 5A-5B 130) and a circuit wiring structure (Figure 5A-5B, 191) on the circuit contact structure (Figure 5A-5B, 155), wherein the guard ring (Figure 3A, 200) comprises a guard active structure (Figure 3A, 205) on the substrate in the second region (Figure 3A, R2), a plurality of guard contact structures (Figure 3A, 255) arranged on the guard active structure, and a guard interconnect structure (Figure 3A, 265) structure on the guard contact structures (Figure 3A, 255), and wherein the guard contact structures (Figure 3A, 255) overlap the plurality of vias (Figure 3A, 271) in a vertical direction perpendicular to a top surface of the substrate. See Figures 1, 3A and 5A-5B and corresponding text, especially paragraphs 43-99.
Hong et al differs from the Claims at hand in that Hong et al disclose a guard interconnect structure, and do not specify a guard wiring structure.
Kabir et al also pertains to semiconductor devices having guard rings, and discloses that interconnect structures comprise vias and lines (wires). See paragraph 74.
It would have been obvious to one of ordinary skill in the art, before the effective date of the invention, to arrive at the presently claimed limitations, as Kabir et al discloses that the interconnect structures of Hong comprise wiring structures.
With respect to Claim 2, Hong discloses the plurality of vias (Figure 3A, 271) contacts the guard wiring structure (Figure 3A, 265). See Figure 3A and corresponding text.
With respect to Claim 3, and the limitation ” wherein a width of a topmost surface of each of the guard contact structures is equal to or less than a topmost surface of the circuit contact structure”, changes in size are prima facie obvious in the absence of unobvious results. See In re Rose, 105 USPQ 237 (CCPA 1955). Moreover, Hong discloses the benefits of optimizing the dimensions in paragraphs 62-63.
With respect to Claim 4, and the limitation “wherein a sum of widths of topmost surfaces of the of guard contact structures is greater than a width of a topmost surface of the circuit contact structure”, changes in size are prima facie obvious in the absence of unobvious results. See In re Rose, 105 USPQ 237 (CCPA 1955). Moreover, Hong discloses the benefits of optimizing the dimensions in paragraphs 62-63.
With respect to Claim 5, Hong discloses “wherein a width of a vertical cross-section of each of the guard contact structures decreases in a direction receding downwards from a topmost surface of the guard contact structure”. See Figure 3A, 255.
With respect to Claim 6, and the limitation “wherein the number of guard contact structures is the same as the number of vias”, the use of two vias (Figure 3A, 271) instead of one would have been obvious to one of ordinary skill in the art as a duplication of parts. See In re Harza, 124 USPQ 378 (CCPA 1960).
With respect to Claim 7, Hong discloses wherein the guard wiring structure contacts a top surface of each of the guard contact structures. See Figure 3A, and 265 and 255.
With respect to Claim 8, Hong further discloses comprising an external guard ring formed on the substrate to surround an external surface of the guard ring. See Figure 3B, 300 and corresponding text.
With respect to Claim 9, Hong further discloses wherein the source/drain region (Figure 5B, 130) is between the circuit contact structure (Figure 5B, 155A) and the circuit active fin (Figure 5B, 105). See Figure 5B and corresponding text.
With respect to Claim 10, Hong further discloses comprising an insulating material structure on a side surface of the guard ring, wherein the insulating material structure comprises a device isolation region (Figure 3A, 181) on side surfaces of the guard active structure and a protective layer (Figure 3A. 254) covering the guard active structure on the device isolation region, and wherein each of the guard contact structures contacts the protective layer. See Figure 3A and corresponding text.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER G GHYKA whose telephone number is (571)272-1669. The examiner can normally be reached Monday-Friday 9-6.
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AGG
September 25, 2026
/ALEXANDER G GHYKA/Primary Examiner, Art Unit 2812
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