DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after allowance or after an Office action under Ex Parte Quayle, 25 USPQ 74, 453 O.G. 213 (Comm'r Pat. 1935). Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant's submission filed on 2/4/2026 has been entered.
This action is responsive to the RCE filed on 2/4/2026. Claims 1-10 and 12-25 are pending and have been examined. Claims 1-2, 4-7, 10, 12-18 and 20 have been amended. Claim 11 has been canceled. Claims 21-25 have been added.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 2-7 are objected to because of the following informalities:
In regards to claim 2, line 1 amend delete “set of” before “one or more” as to correct a minor antecedent basis issue and use language consistent with claim 1 line 4.
In regards to claim 4, line 1 amend delete “set of” before “one or more” as to correct a minor antecedent basis issue and use language consistent with claim 1 line 4.
In regards to claim 5, line 1 amend delete “set of” before “one or more” as to correct a minor antecedent basis issue and use language consistent with claim 1 line 4.
In regards to claim 6, line 1 amend delete “set of” before “one or more” as to correct a minor antecedent basis issue and use language consistent with claim 1 line 4.
In regards to claim 7, line 1 amend delete “set of” before “one or more” as to correct a minor antecedent basis issue and use language consistent with claim 1 line 4.
Claims 3-5 are dependent upon one or more claims above and therefore are similarly objected to on the same basis as one or more claims above.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 7 and 14 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 20-21 of U.S. Patent No. 12,045,617 in view of Liao, PGPUB No. 2002/0026569. The claims of USPAT No. 12,045,617, mostly anticipates the claims of the instant application.
However, claim 20 of USPAT No. 12,045,617 has not taught “…based on an instruction…”.
Liao discloses “…based on an instruction…” ([0076-0077]: wherein a vector load instruction causes a load/store unit to load useful data from memory and add null elements to fill out the rest of the vector to a particular dimension)
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify claim 20 of USPAT No. 12,045,617 to control a memory circuit to load data and fill with null values based on an instruction as taught in Liao. It would have been obvious to one of ordinary skill in the art because it would have been obvious to one of ordinary skill in the art because the instruction uses an improved vector load format which frees bandwidth and memory (Liao [0077]).
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-10 and 12-25 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., abstract idea) without significantly more.
Regarding claim 1:
Subject Matter Eligibility Analysis Step 1:
Claim 1 recites “A circuit device” and thus a machine, one of the four statutory categories of patentable subject matter.
Subject Matter Eligibility Analysis Step 2A Prong 1:
Claim 1 recites “…produce a set of null elements corresponding to the second portion of the array without accessing the memory…” which describe a process that under its broadest reasonable interpretation encompasses mathematical relationships and/or mental processes. That is other than reciting generic computing components (e.g. memory, memory control circuit, storage circuitry, processor core, etc. …) nothing in the claimed elements precludes the steps from practically being performed in the mind and/or with the aid of pen and paper.
For example, the claim discusses generating null elements corresponding to a size of a portion of an array in a first dimension; this would encompass for example generating 32 null elements (e.g. zero values) corresponding to a bit width portion of a vector or array. Thus, the limitation encompasses mathematical relationships and/or mental processes (MPEP 2106.04(a)(2)(I)(A) and (III)).
If a claim, limitation, under its broadest reasonable interpretation, covers performance of a mathematical relationship/mental process in the mind with the aid of pen and paper but for the recitation of generic computer components then it falls within the “Mathematical concepts” and/or “Mental Process” grouping of abstract ideas.
Subject Matter Eligibility Analysis Step 2A Prong 2:
Claim 1 further recites additional elements of
… a memory; a memory control circuit; and a processor core that includes first storage circuitry…based on an instruction…
…configured to store one or more values indicative of a size of a first portion of an array in a first dimension and a size of a second portion of the array in the first dimension…receive a set of data elements… the set of data elements corresponding to the first portion of the array…to provide the set of data elements and the set of null elements
These additional elements do not integrate the abstract idea into a practical application because (a) recites at a high-level of generality the words “apply it” (or an equivalent) with the judicial exception, or use mere instructions to implement the abstract idea on a computer, or merely uses a computer as a tool to perform the abstract idea (See MPEP 2106.05(f)) and (b) recites insignificant extra-solution activity (i.e. data gathering/outputting) of particular data which ties the gathering and outputting to a particular field of use or technological environment (See MPEP 2106.05 (g-h)).
Therefore, claim 1 is directed to the abstract idea.
Subject Matter Eligibility Analysis Step 2B:
The additional elements of claim 1 do not provide significantly more than the abstract idea itself, taken alone and in combination, because (a) uses mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)); (b) recites insignificant extra-solution activity of data gathering/outputting which ties gathering and outputting to a particular field of use or technological environment (See MPEP 2106.05 (g-h)). Furthermore, (b) recites limitations which the courts have deemed to be well-understood, routine and conventional activities that do not provide significantly more (MPEP 2106.05(d)); the courts have recognized that receiving or transmitting data over a network ((Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362), as well as storing and retrieving information in memory are well‐understood, routine, and conventional functionalities (Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93)).
Therefore, based on the discussion of the additional elements above, claim 1 is not patent eligible.
Claim 2, dependent upon claim 1, further recites “…wherein the set of one or more values includes a first value indicative of a combined size of the first portion of the array in the first dimension and the second portion of the array in the first dimension.” The additional limitations recite further details of the types of data stored in claim 1, thus claim 2 is tied to insignificant extra-solution activity of data outputting of particular types of data (particular field of use or technological environment) which are well-understood, routine and conventional activities which cannot provide significantly more (see MPEP 2106.05(d and g-h)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 3, dependent upon claim 2, further recites “…wherein the first value specifies the combined size in terms of a number of bytes.” The additional limitations recite further details of the types of data stored in claims 1-2, thus claim 3 is tied to insignificant extra-solution activity of data outputting of particular types of data (particular field of use or technological environment) which are well-understood, routine and conventional activities which cannot provide significantly more (see MPEP 2106.05(d and g-h)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 4, dependent upon claim 2, further recites “…wherein the set of one or more values includes a second value indicative of the size of the first portion of the array in the first dimension such that the size of the second portion of the array in the first dimension is based on a difference between the first value and the second value”, which recites an additional abstract idea detailing a mathematical relationship of a second value is indicative of a size based on a difference from a first and second value. Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 5, dependent upon claim 4, further recites “…wherein the set of one or more values includes a third value indicative of the second value being in the first dimension”. The additional limitations recite further details of the types of data stored in claims 1-2 and 4, thus claim 5 is tied to insignificant extra-solution activity of data outputting of particular types of data (particular field of use or technological environment) of data which are well-understood, routine and conventional activities, which cannot provide significantly more (see MPEP 2106.05(d and g-h)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 6, dependent upon claim 1, further recites “…wherein the set of one or more values is indicative of a size of the first portion of the array in a second dimension and a size of the second portion of the array in the second dimension.” The additional limitations recite further details of the types of data stored in claim 1, thus claim 6 is tied to insignificant extra-solution activity of data outputting of particular types of data (particular field of use or technological environment), which are well-understood, routine and conventional activities, which cannot provide significantly more (see MPEP 2106.05(d and g-h)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 7, dependent upon claim 1, further recites “…wherein the set of one or more values includes at least one value indicative of a value for the set of null elements.” The additional limitations recite further details of the types of data stored in claim 1, thus claim 7 is tied to insignificant extra-solution activity of data outputting of particular types of data (particular field of use or technological environment), which are well-understood, routine and conventional activities, which cannot provide significantly more (see MPEP 2106.05(d and g-h)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 8, dependent upon claim 1, further recites “…wherein the instruction is a stream open instruction that specifies the register”. The additional limitations tie the abstract idea to using mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 9, dependent upon claim 1, further recites “…wherein the memory control circuit is configured to provide the set of data elements and the set of null elements as a vector...” The additional limitations recite further details of the types of data provided in claim 1, thus claim 9 is tied to insignificant extra-solution activity of data outputting of particular types of data (particular field of use or technological environment, e.g. vector data), which are well-understood, routine and conventional activities which cannot provide significantly more (see MPEP 2106.05(d and g-h)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 10, dependent upon claim 1, further recites “…wherein the memory control circuit includes: an interface configured to couple to the memory and configured to receive from the memory the set of data elements corresponding to the first portion of the array from the memory; second storage circuity coupled to the interface and configured to store the set of data elements corresponding to the first portion of the array from the memory; and a set of multiplexers coupled between the second storage circuity and the processor core.” The additional limitations tie the abstract idea to using mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)). The additional limitations also recite insignificant extra-solution activity of data gathering/outputting, which are well-known, routine and conventional activities (See MPEP 2106.05 (d and g)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 12, dependent upon claim 1, further recites “…wherein the memory is a cache memory.” While, claim 13 is dependent upon claim 1, further recites “…wherein the memory is a level-two (L2) cache memory.” The additional limitations of both claims tie the abstract idea to using mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)).
Claim 14 is similarly rejected on the same basis as claim 1 above. (Note: Claim 14 differs from claim 1 in that it states “determining, based on a set of one or more values, sizes”, while claim 1 state “storing values indicative of the sizes”. Thus, the determining step in claim 14 would be considered an abstract idea of a mental process at step 2A prong one because the determining step would be an observation or evaluation based on the values)
Claims 15-20 are similarly rejected on the same basis as claim 2 and 4-9.
Claim 21 is similarly rejected on the same basis as claims 1 and 6 above. (Note: Claim 21 differs from claim 1 in that it states “determining, based on a set of one or more parameters, sizes”, while claim 1 state “storing values indicative of the sizes”. Thus, the determining step in claim 21 would be considered an abstract idea of a mental process at step 2A prong one because the determining step would be an observation or evaluation based on parameters)
Claims 22-25 are similarly rejected on the same basis as claim 2, 4, 6-7 and 10.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8 and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In regards to claim 8, line 2 the limitation “the register” lacks clarity. The limitation lacks clarity because it lacks proper antecedent basis as there is no prior recitation of “a register”.
In regards to claim 19, line 2 the limitation “the register” lacks clarity. The limitation lacks clarity because it lacks proper antecedent basis as there is no prior recitation of “a register”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 14-16 and 18-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liao, PGPUB No. 2002/0026569 (cited on IDS filed on 7/22/2024).
In regards to claim 14, Liao discloses A method (see [0014]) comprising: determining, based on a set of one or more values, a size of a first portion of an array in a first dimension and a size of a second portion of the array in the first dimension ([0076-0077 and 0081-0082]: wherein position bits (element 126) and a destination vector register location (element 130) are used to determine a size of a first portion of useful data and a size of a second portion of filler data in a dimension of a vector because the position bits indicate an ending address of useful data to be loaded into a destination vector register from a starting address (e.g. if destination vector, identified by field element 130, has a dimension of 64 and position bits are used to load 32 elements into destination vector, then size of first portion of array is 32, and then the rest of the vector would be filled with 32 constant elements for a vector with a dimension of 64) (also see [0016, 0018 and Fig. 2] for further clarity and discussion of dimensions of vectors)) receiving an instruction by a processor core ([0075-0076]: wherein vector load instruction (element 118) is received by microprocessor (see Fig. 3))and based on the instruction: causing a memory control circuit to receive from a memory a set of data elements corresponding to the first portion of the array ([0076-0077]: wherein when the vector load instruction is executed a load/store unit loads useful data corresponding to the first portion of the array) causing the memory control circuit to produce a set of null elements corresponding to the second portion of the array without accessing the memory ([0076-0077]: wherein the load/store unit produces a set of filler data corresponding to the second portion of the array without accessing memory) and causing the memory control circuit to provide the set of data elements corresponding to the first portion of the array and the set of null elements corresponding to the second portion of the array to the processor core. ([0075-0077]: wherein the load/store unit provides the useful data elements and the filler data of constant values to vector register of microprocessor (See Figs. 2-3))
In regards to claim 15, Liao discloses The method of claim 14 (see rejection of claim 14 above) wherein the set of one or more values includes: a first value indicative of a combined size of the first portion of the array in the first dimension and the second portion of the array in the first dimension ([0076-0078]: wherein a destination vector register location (element 130) is indicative of a combined size of the first and second portion of the array in the first dimension because it identifies a destination vector of a particular length (e.g. if a destination vector location identified is a dimension of 64 the combined size equals 64) and a second value indicative of the size of the first portion of the array in the first dimension. ([0076-0078]: wherein position bits (element 126) indicate a size of the first portion of useful data in the vector)
In regards to claim 16, the combination of Liao and Shimp discloses The method of claim 15 (see rejection of claim 15 above) wherein the set of one or more values includes a third value indicative of the second value being in the first dimension. (Liao [0076-0078]: wherein the source address (element 124) is a value indicative that the position bits are in the first dimension as the position bits indicate an ending address offset from said source address)
In regards to claim 18, Liao discloses The method of claim 14 (see rejection of claim 14 above) wherein the set of values includes at least one value indicative of a value for the set of null elements. ([0076-0078]: value field (element 128) indicates the value for the null elements)
In regards to claim 19, Liao discloses The method of claim 14 (see rejection of claim 14 above) wherein the instruction is a stream open instruction that specifies the register. ([0044-0046 and 0076-0078]: wherein the load instruction is a stream open instruction as it loads a stream of data, from enabled open cache which is not blocked or disabled, into a destination register)
In regards to claim 20, Liao discloses The method of claim 14 (see rejection of claim 14 above) wherein the set of data elements corresponding to the first portion and the set of null elements corresponding to the second portion are provided to the processor core as a vector. ([0076-0078]: wherein the set of data elements corresponding to the useful portion and filler portion are provided as a vector to be stored in destination vector register)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 7-9 and 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liao, and further in view of Shimp, USPAT No. 3,916,388.
In regards to claim 1, Liao discloses A circuit device ([0036]: wherein processing system is disclosed) comprising: a memory ([0036 and Fig. 3]) a memory control circuit ([0036 and Fig. 3]: wherein a load/store unit is disclosed) processor core ([0036]: microprocessor core) one or more values indicative of a size of a first portion of an array in a first dimension and a size of a second portion of the array in the first dimension ([0008-0009, 0076-0077 and 0081-0082]: wherein position bits (element 126) and a destination vector register location (element 130) are indicative of a size of a first portion of useful data and a size of a second portion of filler data in a dimension of a vector because the position bits indicate an ending address of useful data to be loaded into a destination vector register from a starting address (e.g. if destination vector, identified based on field 130, has a dimension of 64 and position bits are used to load 32 elements into destination vector, then size of first portion of array is 32, and then the rest of the vector would be filled with 32 constant elements for a vector with a dimension of 64) (also see [0016, 0018 and Fig. 2] for further clarity and discussion of dimensions of vectors)) receiving an instruction by a processor core ([0075-0076]: wherein vector load instruction (element 118) is received by microprocessor (see Fig. 3))wherein the processor core is configured to: based on the instruction: cause the memory control circuit to receive a set of data elements from the memory, the set of data elements corresponding to the first portion of the array ([0076-0077]: wherein when the vector load instruction is executed a load/store unit loads useful data corresponding to the first portion of the array) causing the memory control circuit to produce a set of null elements corresponding to the second portion of the array without accessing the memory ([0076-0077]: wherein the load/store unit produces a set of filler data corresponding to the second portion of the array without accessing memory) and causing the memory control circuit to provide the set of data elements and the set of null elements to the processor core. ([0075-0077]: wherein the load/store unit provides the useful data elements and the filler data of constant values to vector register of microprocessor (See Figs. 2-3))
Liao does not disclose a processor that includes first storage circuitry configured to store one or more values. Liao discloses using an instruction which stores values indicative of sizes of portions of a vector array. However, Liao does not disclose storing said values in storage circuitry.
Shimp discloses a processor that includes first storage circuitry configured to store one or more values indicative of a size of a first portion and a size of a second portion of data (Column 5, lines 54-67 and Column 9, lines 1-28: wherein control word register includes length field (bits 5-7) indicating a number of bytes to be read and destination address/format (bits 16-20) indicate a size of a second portion because if destination is storing less than 8 bytes based on length field then the rest of the destination is filled with zeroes based on bit 20)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the processor of Liao to include a register to store size information as taught in Shimp. It would have been obvious to one of ordinary skill in the art because it would have been applying a known technique (storing one or more size indicators in a control register for a load instruction as taught in Shimp) to a known device (processor of Liao which performs load instructions which indicate one or more size indicators) ready for improvement to yield predictable results (storing one or more size indicators in a control register for a load instruction to load useful data and filler data into a vector) for the benefit of storing instruction operands in a single register, rather than instructions which keeps instructions compact, allowing more to fit into an instruction cache (MPEP 2143, Example D).
In regards to claim 2, the combination of Liao and Shimp discloses The circuit device of claim 1 (see rejection of claim 1 above) wherein the set of one or more values includes a first value indicative of a combined size of the first portion of the array in the first dimension and the second portion of the array in the first dimension (Liao [0008-0009, 0076-0078 and 0081]: wherein a destination vector register location (element 130) is indicative of a combined size of the first and second portion of the array in the first dimension because it identifies a destination vector of a particular length (e.g. if a destination vector location identified is a dimension of 64 the combined size equals 64)) and a second value indicative of the size of the first portion of the array in the first dimension. (Liao [0076-0078]: wherein position bits (element 126) indicate a size of the first portion of useful data in the vector)
In regards to claim 3, the combination of Liao and Shimp discloses The circuit device of claim 2 (see rejection of claim 2 above) wherein the first value specifies the combined size in terms of a number of bytes. (Liao [0008-0009, 0076-0078 and 0081]: wherein a destination vector register location specifies a destination vector including 64 32-bit elements, and thus specifies 256 bytes)
In regards to claim 4, the combination of Liao and Shimp discloses The circuit device of claim 2 (see rejection of claim 2 above) wherein the set of one or more values includes a second value indicative of the size of the first portion of the array in the first dimension such that the size of the second portion of the array in the first dimension is based on a difference between the first value and the second value. (Liao [0076-0078]: wherein position bits (element 126) indicate a size of the first portion of useful data in the vector such that the size of the filler portion of the array in the vector is based on a difference between total dimension indicated by the destination vector and the useful data)
In regards to claim 5, the combination of Liao and Shimp discloses The circuit device of claim 4 (see rejection of claim 4 above) wherein the set of one or more values includes a third value indicative of the second value being in the first dimension. (Liao [0076-0078]: wherein the source address (element 124) is a value indicative that the position bits are in the first dimension as the position bits indicate an ending address offset from said source address)
In regards to claim 7, the combination of Liao and Shimp discloses The circuit device of claim 1 (see rejection of claim 1 above) wherein the set of one or more values includes at least one value indicative of a value for the set of null elements. (Liao [0076-0078]: value field (element 128) indicates the value for the null elements)
In regards to claim 8, the combination of Liao and Shimp discloses The circuit device of claim 1 (see rejection of claim 1 above) wherein the instruction is a stream open instruction that specifies the register. (Liao [0044-0046 and 0076-0078]: wherein the load instruction is a stream open instruction as it loads a stream of data, from enabled open cache which is not blocked or disabled, into a destination register)
In regards to claim 9, the combination of Liao and Shimp discloses The circuit device of claim 1 (see rejection of claim 1 above) wherein the memory control circuit is configured to provide the set of data elements and the set of null elements as a vector. (Liao [0076-0078]: wherein the set of data elements corresponding to the useful portion and filler portion are provided as a vector to be stored in destination vector register by load/store unit)
In regards to claim 12, the combination of Liao and Shimp discloses The circuit device of claim 1 (see rejection of claim 1 above) wherein the memory is a cache memory. (Liao [0036 and 0044-0046]: cache memory (See Fig. 3))
In regards to claim 13, the combination of Liao and Shimp discloses The circuit device of claim 1 (see rejection of claim 1 above) wherein the memory is a level-two (L2) cache memory. (Liao [0036 and 0044-0046]: L2 cache memory (See Fig. 3))
Allowable Subject Matter
Claims 6, 10 and 17 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 101, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claims 21-25 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 101, set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record, alone or in combination, fail to disclose or render obvious claim 6 filed on 2/4/2026. The prior art of record has not taught either individually or in combination and together with all other claimed features “The circuit device of claim 1, wherein the set of one or more values is indicative of a size of the first portion of the array in a second dimension and a size of the second portion of the array in the second dimension” as claimed in claim 6.
The closest prior art of record, Liao discloses using one or more values of a load instruction to identify a first portion of useful data to be stored in a dimension of a vector and a second portion of constant values to be stored in the dimension of the vector. However, Liao does not disclose storing nor determining one or more values indicating a size of the first and second portions of the array in a second dimension as claimed in claim 6.
Furthermore, while some limitations may be broadly disclosed in the references above, the specific combination of limitations would not be obvious as claimed absent impermissible hindsight.
Claims 17 and 21 are similarly allowable for the same reasons as claim 6 above.
Claims 22-25 are dependent upon claim 21 and therefore are similarly allowable for the same reasons as claim 21.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record, alone or in combination, fail to disclose or render obvious claim 10 filed on 2/4/2026. The prior art of record has not taught either individually or in combination and together with all other claimed features “The circuit device of claim 1, wherein the memory control circuit includes: an interface configured to couple to the memory and configured to receive from the memory the set of data elements corresponding to the first portion of the array; second storage circuity coupled to the interface and configured to store the set of data elements corresponding to the first portion of the array; and a set of multiplexers coupled between the second storage circuity and the processor core” as claimed in claim 10.
The closest prior art of record, Liao discloses using a load/store unit to load data from memory using buses and interconnects. However, Liao does not disclose second storage circuity coupled to the interface and configured to store the set of data elements corresponding to the first portion of the array; and a set of multiplexers coupled between the second storage circuity as claimed in claim 10.
Furthermore, while some limitations may be broadly disclosed in the references above, the specific combination of limitations would not be obvious as claimed absent impermissible hindsight.
Conclusion
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/COURTNEY P SPANN/ Primary Examiner, Art Unit 2183