Prosecution Insights
Last updated: August 17, 2026
Application No. 18/779,259

PACKET PROCESSING FOR CLUSTERED CONTAINERS USING INTERNAL BRIDGING AND AN OFFLOAD ARCHITECTURE

Non-Final OA §103
Filed
Jul 22, 2024
Examiner
LEE, CHUN KUAN
Art Unit
2181
Tech Center
2100 — Computer Architecture & Software
Assignee
Dell Products L.P.
OA Round
3 (Non-Final)
68%
Grant Probability
Favorable
3-4
OA Rounds
1y 3m
Est. Remaining
72%
With Interview

Examiner Intelligence

Grants 68% — above average
68%
Career Allowance Rate
465 granted / 681 resolved
+13.3% vs TC avg
Minimal +4% lift
Without
With
+3.8%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
19 currently pending
Career history
708
Total Applications
across all art units

Statute-Specific Performance

§101
2.5%
-37.5% vs TC avg
§103
73.5%
+33.5% vs TC avg
§102
5.3%
-34.7% vs TC avg
§112
8.1%
-31.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 681 resolved cases

Office Action

§103
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . CONTINUED EXAMINATION UNDER 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 6/12/2026 has been entered. RESPONSE TO ARGUMENTS Applicant's arguments filed 6/12/2026 have been fully considered but they are not persuasive. In response to applicant’s arguments with regard to the independent claim 1 rejected under 35 U.S.C. 103(a) that the combination of the references does not teach/suggest the claimed feature “… selecting, using an application executing on a container in a pod on a physical host, a transmission interface associated with the pod over which to transmit a packet based on whether the packet is an internal packet or an external packet … wherein packets are processed either by the host bridge or resources on the DPU …” because the combination of Tang, Sharma and Gadi do not teach the above claimed features; applicant's arguments have fully been considered, but are not found to be persuasive. The examiner respectfully disagrees, and to further clarify, by combining Sharma’s selecting accordingly (e.g. associated with selecting/using virtual network interface (212)-(213) or virtual function (27A) by pod (202A) for communication in Fig. 3: [0114]; [0122]; [0167]); and wherein packets are processed by either one or another (e.g. associated processing by virtual router or virtual function: Fig. 3; [0014]; [0114]; [0118]-[0122]; [0167]) (Fig. 1; Fig. 3; Fig. 5; [0008]; [0014]; [0072]; [0110]-[0122]; and [0167]) and Gadi’s being processed by the resources on the DPU (e.g. associated with workload being performed using resources of DPU device (109): [0030]) (Fig. 2; [0030]; and [0037]-[0039]) with Tang’s operating with, using an application executing on a container in a pod on a physical host, a transmission interface associated with the pod over which to transmit a packet (e.g. associated with transmission of data between Pods via corresponding interfaces in Fig. 3-4 and Fig. 7-8: [0026]-[0027]; [0059]-[0063]; and [0070]-[0080]) based on whether the packet is an internal packet (e.g. associated with intra-node data transfer: Fig. 3-4; [0059]-[0063]) or an external packet (e.g. associated with communication between nodes executing on different host computers: Fig. 7-8, [0070]-[0080]) (Fig. 3-4; Fig. 6-8; [0003]-[0009]; [0026]-[0030]; [0034]; [0059]-[0063]; and [0069]-[0080]; [0090]), the resulting combination of the references would further teach/suggest the above claimed features. Furthermore, Tang does teach/suggest the determination of whether data traffic is external traffic or internal traffic prior to transmission as source/transmitter would have determined destination/receiver of the packet prior to transmission when the packet is formed, where the packet is then either communicated via external traffic (e.g. associated with communication between nodes on different host computer) or internal traffic (e.g. associated with communication between nodes on same host computer/intra-node data transferring). Additionally, Sharma does teach/suggest transmitting data traffic via direct interface to virtual function (27A) (i.e. transmission that does not require use of bridge/router: Fig. 3: [0114]; [0122]; [0167]). As applicant appears to be applying the above arguments for independent claim 1 towards independent claim 20, the examiner will also apply the above response for independent claim 1 towards independent claim 20. . I. REJECTIONS BASED ON PRIOR ART Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Tang et al. (US Pub.: 2023/0231827) in view of Sharma et al. (US Pub.: 2024/0422107) and Gadi et al. (US Pub.: 2024/0241728). As per claim 1, Tang teaches/suggests a method for processing packets, comprising: operating with, using an application executing on a container in a pod on a physical host, a transmission interface associated with the pod over which to transmit a packet (e.g. associated with transmission of data between Pods via corresponding interfaces in Fig. 3-4 and Fig. 7-8: [0026]-[0027]; [0059]-[0063]; and [0070]-[0080]) based on whether the packet is an internal packet (e.g. associated with intra-node data transfer: Fig. 3-4; [0059]-[0063]) or an external packet (e.g. associated with communication between nodes executing on different host computers: Fig. 7-8, [0070]-[0080]), wherein each pod on the physical host comprises transmission interface, the transmission interface comprising a virtual Ethernet interface (e.g. associated with virtual Ethernet interface in Fig. 3-4 and Fig. 7-8; [0059]-[0060]; [0070]-[0077]), wherein internal packets are destined for another pod on the physical host (e.g. associated with intra-node data transfer: Fig. 3-4; [0059]-[0063]) and external packets are destined for another pod on a different physical host (e.g. associated with communication between nodes executing on different host computers: Fig. 7-8, [0070]-[0080]), wherein internal packets are transmitted over the virtual Ethernet interface and are processed by a host bridge (e.g. associated with transfer over virtual Ethernet interface (362, 364) and OVS Bridge (330): Fig. 3-4; [0059]-[0063]; [0090]), wherein external packets are transmitted accordingly (e.g. associated with communication between nodes executing on different host computers: Fig. 7-8, [0070]-[0080]), being processed by the host bridge (e.g. associated with process for transferring via OVS Bridge (330): Fig. 3-4; [0059]-[0063]; [0090]), wherein the transmission interface is the virtual Ethernet interface (e.g. associated with virtual Ethernet interface in Fig. 3-4 and Fig. 7-8; [0059]-[0060]; [0070]-[0077]); receiving the packet by the host bridge in the physical host (e.g. associated with bridge (330) in Fig. 3-4), wherein the packet is destined for a second container on a second pod in executing on the physical host (e.g. associated with bridge (330) receiving data transmitted by Pod1A (320) destined for Pod1B (322)/Pod2A (324) in Fig. 3-4: [0059]-[0063]); and transmitting, by the host bridge, the packet to a second interface, wherein the second pod is associated with the second interface (e.g. associated with bridge (330) transmitting the received data to Pod1B (322)/Pod2A (324) in Fig. 3-4: [0059]-[0063]) (Fig. 3-4; Fig. 6-8; [0003]-[0009]; [0026]-[0030]; [0034]; [0059]-[0063]; [0069]-[0080]; and [0090]). Tang do not teach the method comprising: selecting accordingly, comprising a set of transmission interfaces, the set of transmission interfaces comprising: one of a plurality virtual function, each mapped to a data processing unit (DPU), executing using a processor on the physical host, being transmitted over one of the plurality of virtual functions and are offload from the processor on the physical host and processed using resources on the DPU, and wherein packets are processed by either one or the resources on the DPU. Sharma teaches/suggests a method comprising: selecting accordingly (e.g. associated with selecting/using virtual network interface (212)-(213) or virtual function (27A) by pod (202A) for communication in Fig. 3: [0114]; [0122]; [0167]); comprising a set of transmission interfaces (e.g. associated with interfaces for virtual network interface (212)-(213) and virtual function (27A) in Fig. 3: [0114]; [0122]; and [0167]), the set of transmission interfaces comprising: one of a plurality virtual function, each operating accordingly (e.g. associated with virtual function (27A) in Fig. 3; [0114]; [0167]); executing using a processor on the physical host ([0014]), being transmitted over one of the plurality of virtual functions and operating accordingly (e.g. associated processing by Network Interrace Card and transmitting over virtual functions (27A, 27B): [0114]; [0167]), wherein packets are processed by either one or another (e.g. associated processing by virtual router or virtual function: Fig. 3; [0014]; [0114]; [0118]-[0122]; [0167]) (Fig. 1; Fig. 3; Fig. 5; [0008]; [0014]; [0072]; [0110]-[0122]; and [0167]). Gadi teach/suggest a method comprising: being mapped to a data processing unit (DPU) (e.g. Fig. 2, ref. 109), being offload from the processor on the physical host and processed using resources on the DPU (e.g. associated being offloaded from host device (106) and being processed using resources on the DPU (109) in Fig. 2; [0030]), and being processed by the resources on the DPU (e.g. associated with workload being performed using resources of DPU device (109): [0030]) (Fig. 2; [0030]; and [0037]-[0039]). It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Sharma’s interfacing architecture and Gadi’s DPU into Tang’s method for the benefit of simplifying the configuration and reconfiguration of virtual router (Sharma, [0012]) and offloading workload to the DPU (Gadi, [0030]) to obtain the invention as specified in claim 1. As per claim 2, Tang, Sharma and Gadi teach/suggest all the claimed features of claim 1 above, where Tang, Sharma and Gadi further teach/suggest the method further comprising: selecting, using the application, a second transmission interface from the set of transmission interfaces over which to transmit a second packet, wherein the second transmission interface is the one of the plurality of virtual functions; receiving the second packet via a representor port on the DPU operatively connected to a physical host, wherein the physical host is connected to the DPU using a Peripheral Component Interconnect Express (PCIe) connection, wherein the PCIe connection is associated with the one of the plurality of virtual functions; wherein the one or the plurality of virtual functions is mapped to the representor port, in response to receiving the packet, processing the packet using a hardware switch pipeline in the DPU; and initiating transmission of the packet towards its intended destination using the exact match flow entry (Tang, Fig. 3-8; [0003]-[0009]; [0026]-[0030]; [0034]; [0059]-[0063]; [0069]-[0080]; [0090]; Sharma, Fig. 1; Fig. 3; Fig. 5; [0008]; [0014]; [0046]; [0072]; [0078]-[0079]; [0110]-[0122]; [0167]; and Gadi, Fig. 2; [0030]; [0037]-[0039]). As per claim 3, Tang, Sharma, and Gadi teach/suggest all the claimed features of claim 2 above, where Tang, Sharma, and Gadi further teach/suggest the method comprising wherein the intended destination of the second packet is external to the physical host and the DPU (Tang, Fig. 3-8; [0003]-[0009]; [0026]-[0030]; [0034]; [0059]-[0063]; [0069]-[0080]; [0090]; Sharma, Fig. 1; Fig. 3; Fig. 5; [0008]; [0014]; [0046]; [0072]; [0078]-[0079]; [0110]-[0122]; [0167]; and Gadi, Fig. 2; [0030]; [0037]-[0039]). As per claim 4, Tang, Sharma, and Gadi teach/suggest all the claimed features of claim 2 above, where Tang, Sharma, and Gadi further teach/suggest the method comprising wherein the processing the packet comprises using a plurality of match/action tables to identify an exact match flow entry for the packet, wherein the plurality of match/action tables do not contain any exact match flow entries that are not exact match flow entries (Tang, Fig. 3-8; [0003]-[0009]; [0026]-[0030]; [0034]; [0059]-[0063]; [0069]-[0080]; [0090]; Sharma, Fig. 1; Fig. 3; Fig. 5; [0008]; [0014]; [0046]; [0072]; [0078]-[0079]; [0110]-[0122]; [0167]; and Gadi, Fig. 2; [0030]; [0037]-[0039]), wherein it would have been obvious to one of ordinary skilled in the art that the resulting combination of the references further teaches the above claimed features as data is proper communicated for processing. As per claim 5, Tang, Sharma, and Gadi teach/suggest all the claimed features of claim 4 above, where Tang, Sharma, and Gadi further teach/suggest the method comprising wherein the plurality of match/action tables are organized in a hierarchical table structure (Tang, Fig. 3-8; [0003]-[0009]; [0026]-[0030]; [0034]; [0050]-[0051]; [0057]-[0063]; [0069]-[0080]; [0090]; Sharma, Fig. 1; Fig. 3; Fig. 5; [0008]; [0014]; [0046]; [0072]; [0078]-[0079]; [0110]-[0122]; [0167]; and Gadi, Fig. 2; [0030]; and [0037]-[0039]), wherein it would have been obvious to one of ordinary skilled in the art that the resulting combination of the references further teaches the above claimed features as data is proper communicated for processing. As per claim 6, Tang, Sharma, and Gadi teach/suggest all the claimed features of claim 5 above, where Tang, Sharma, and Gadi further teach/suggest the method comprising wherein the hierarchical table structure comprises a layer 2 source table, a layer 2 destination table, and a layer 3 routing flows table (Tang, Fig. 3-8; [0003]-[0009]; [0026]-[0030]; [0034]; [0050]-[0051]; [0057]-[0063]; [0069]-[0080]; [0090]; Sharma, Fig. 1; Fig. 3; Fig. 5; [0008]; [0014]; [0046]; [0072]; [0078]-[0079]; [0110]-[0122]; [0167]; and Gadi, Fig. 2; [0030]; [0037]-[0039]), wherein it would have been obvious to one of ordinary skilled in the art that the resulting combination of the references further teaches the above claimed features as data is proper communicated for processing. As per claim 7, Tang, Sharma, and Gadi teach/suggest all the claimed features of claim 4 above, where Tang, Sharma, and Gadi further teach/suggest the method comprising wherein the plurality of match/action tables are content addressable memory tables and wherein the exact match flow entry is stored on one of the content addressable memory tables (Tang, Fig. 3-8; [0003]-[0009]; [0026]-[0030]; [0034]; [0050]-[0051]; [0057]-[0063]; [0069]-[0080]; [0090]; Sharma, Fig. 1; Fig. 3; Fig. 5; [0008]; [0014]; [0046]; [0072]; [0078]-[0079]; [0110]-[0122]; [0167]; and Gadi, Fig. 2; [0030]; [0037]-[0039]), wherein it would have been obvious to one of ordinary skilled in the art that the resulting combination of the references further teaches the above claimed features as data is proper communicated for processing. As per claim 8, Tang, Sharma, and Gadi teach/suggest all the claimed features of claim 2 above, where Tang, Sharma, and Gadi further teach/suggest the method further comprising: prior to receiving the second packet, receiving a third packet by the DPU; in response to receiving the third packet, making a first determination that there is no exact match flow entry in the hardware switch pipeline; in response to the first determination, classifying, in the DPU, the third packet as a data packet; in response to the classifying of the third packet: identifying, using a software data plane in the DPU, a forwarding information base (FIB) entry to be used to transmit the third packet towards its intended destination; identifying, using the software data plane, a flow associated with the third packet; initiating, using the software data plane, programming of the exact match flow entry in the hardware switch pipeline; and initiating, using the software data plane, transmission of the third packet towards its intended destination using the FIB entry and the hardware switch pipeline, wherein the packet is associated with the flow (Tang, Fig. 3-6; Fig. 6-8; [0003]-[0009]; [0026]-[0030]; [0034]; [0050]-[0051]; [0057]-[0063]; [0069]-[0080]; [0090]; Sharma, Fig. 1; Fig. 3; Fig. 5; [0008]; [0014]; [0046]; [0072]; [0078]-[0079]; [0110]-[0122]; [0167]; and Gadi, Fig. 2; [0030]; [0037]-[0039]), wherein it would have been obvious to one of ordinary skilled in the art that the resulting combination of the references further teaches the above claimed features as data is proper communicated for processing. As per claim 9, Tang, Sharma, and Gadi teach/suggest all the claimed features of claim 8 above, where Tang, Sharma, and Gadi further teach/suggest the method further comprising: prior to receiving the third packet, receiving a fourth packet by the DPU; in response to receiving the fourth packet, making a second determination that there is no exact match flow entry in the hardware switch pipeline in the DPU; and in response to the second determination, classifying, in the DPU, the fourth packet as a control plane packet, wherein the control plane packet comprises a Border Gateway Protocol (BGP) message; in response to the classifying of the fourth packet: processing, by a control plane in the DPU, the fourth packet to obtain a route entry, wherein the route entry is stored in a routing information based (RIB) in the control plane, and wherein information in the route entry is subsequently stored in the software data plane in the FIB entry (Tang, Fig. 3-6; Fig. 6-8; [0003]-[0009]; [0026]-[0030]; [0034]; [0050]-[0051]; [0057]-[0063]; [0069]-[0080]; [0090]; Sharma, Fig. 1; Fig. 3; Fig. 5; [0008]; [0014]; [0046]; [0072]; [0078]-[0079]; [0110]-[0122]; [0167]; and Gadi, Fig. 2; [0030]; [0037]-[0039]), wherein it would have been obvious to one of ordinary skilled in the art that the resulting combination of the references further teaches the above claimed features as data is proper communicated for processing. As per claim 10, Tang, Sharma, and Gadi teach/suggest all the claimed features of claim 8 above, where Tang, Sharma, and Gadi further teach/suggest the method comprising 10. The method of claim 8, wherein the exact match flow entry is not programmed until the hardware switch pipeline until after the packet is received by the DPU (Tang, Fig. 3-6; Fig. 6-8; [0003]-[0009]; [0026]-[0030]; [0034]; [0050]-[0051]; [0057]-[0063]; [0069]-[0080]; [0090]; Sharma, Fig. 1; Fig. 3; Fig. 5; [0008]; [0014]; [0046]; [0072]; [0078]-[0079]; [0110]-[0122]; [0167]; and Gadi, Fig. 2; [0030]; [0037]-[0039]), wherein it would have been obvious to one of ordinary skilled in the art that the resulting combination of the references further teaches the above claimed features as data is proper communicated for processing. As per claim 11, Tang, Sharma, and Gadi teach/suggest all the claimed features of claim 8 above, where Tang, Sharma, and Gadi further teach/suggest the method comprising wherein programming of the exact match flow entry in the hardware switch pipeline comprises storing the exact match flow entry in any available storage location in the hardware switch pipeline (Tang, Fig. 3-6; Fig. 6-8; [0003]-[0009]; [0026]-[0030]; [0034]; [0050]-[0051]; [0057]-[0063]; [0069]-[0080]; [0090]; Sharma, Fig. 1; Fig. 3; Fig. 5; [0008]; [0014]; [0046]; [0072]; [0078]-[0079]; [0110]-[0122]; [0167]; and Gadi, Fig. 2; [0030]; [0037]-[0039]), wherein it would have been obvious to one of ordinary skilled in the art that the resulting combination of the references further teaches the above claimed features as data is proper communicated for processing. As per claim 12, Tang, Sharma, and Gadi teach/suggest all the claimed features of claim 11 above, where Tang, Sharma, and Gadi further teach/suggest the method comprising wherein the programming of the exact match flow entry does not require any reordering of any previously stored exact match flow entries in the hardware switch pipeline (Tang, Fig. 3-6; Fig. 6-8; [0003]-[0009]; [0026]-[0030]; [0034]; [0050]-[0051]; [0057]-[0063]; [0069]-[0080]; [0090]; Sharma, Fig. 1; Fig. 3; Fig. 5; [0008]; [0014]; [0046]; [0072]; [0078]-[0079]; [0110]-[0122]; [0167]; and Gadi, Fig. 2; [0030]; [0037]-[0039]), wherein it would have been obvious to one of ordinary skilled in the art that the resulting combination of the references further teaches the above claimed features as data is proper communicated for processing. As per claim 13, Tang, Sharma, and Gadi teach/suggest all the claimed features of claim 8 above, where Tang, Sharma, and Gadi further teach/suggest the method comprising wherein the classifying is performed using vector packet processing (VPP) (Tang, Fig. 3-6; Fig. 6-8; [0003]-[0009]; [0026]-[0030]; [0034]; [0050]-[0051]; [0057]-[0063]; [0069]-[0080]; [0090]; Sharma, Fig. 1; Fig. 3; Fig. 5; [0008]; [0014]; [0046]; [0072]; [0078]-[0079]; [0110]-[0122]; [0167]; and Gadi, Fig. 2; [0030]; [0037]-[0039]), wherein it would have been obvious to one of ordinary skilled in the art that the resulting combination of the references further teaches the above claimed features as data is proper communicated for processing. As per claim 14, Tang, Sharma, and Gadi teach/suggest all the claimed features of claim 13 above, where Tang, Sharma, and Gadi further teach/suggest the method comprising wherein a host control plane plug-in executing on the physical host configures the software data plane on the DPU to perform the VPP (Tang, Fig. 3-6; Fig. 6-8; [0003]-[0009]; [0026]-[0030]; [0034]; [0050]-[0051]; [0057]-[0063]; [0069]-[0080]; [0090]; Sharma, Fig. 1; Fig. 3; Fig. 5; [0008]; [0014]; [0046]; [0072]; [0078]-[0079]; [0110]-[0122]; [0167]; and Gadi, Fig. 2; [0030]; [0037]-[0039]), wherein it would have been obvious to one of ordinary skilled in the art that the resulting combination of the references further teaches the above claimed features as data is proper communicated for processing. As per claim 15, Tang, Sharma, and Gadi teach/suggest all the claimed features of claim 14 above, where Tang, Sharma, and Gadi further teach/suggest the method comprising wherein the host control plane plug-in associates the pod with the one of the plurality of virtual functions (Tang, Fig. 3-6; Fig. 6-8; [0003]-[0009]; [0026]-[0030]; [0034]; [0050]-[0051]; [0057]-[0063]; [0069]-[0080]; [0090]; Sharma, Fig. 1; Fig. 3; Fig. 5; [0008]; [0014]; [0046]; [0072]; [0078]-[0079]; [0110]-[0122]; [0167]; and Gadi, Fig. 2; [0030]; [0037]-[0039]), wherein it would have been obvious to one of ordinary skilled in the art that the resulting combination of the references further teaches the above claimed features as data is proper communicated for processing. As per claim 16, Tang, Sharma, and Gadi teach/suggest all the claimed features of claim 2 above, where Tang, Sharma, and Gadi further teach/suggest the method comprising wherein the pod comprises a plurality of containers, wherein the container is one of the plurality of containers, wherein the plurality of containers all use the one of the plurality of virtual functions to transmit packets to the DPU (Tang, Fig. 3-6; Fig. 6-8; [0003]-[0009]; [0026]-[0030]; [0034]; [0050]-[0051]; [0057]-[0063]; [0069]-[0080]; [0090]; Sharma, Fig. 1; Fig. 3; Fig. 5; [0008]; [0014]; [0046]; [0072]; [0078]-[0079]; [0110]-[0122]; [0167]; and Gadi, Fig. 2; [0030]; [0037]-[0039]), wherein it would have been obvious to one of ordinary skilled in the art that the resulting combination of the references further teaches the above claimed features as data is proper communicated for processing. As per claim 17, Tang, Sharma and Gadi teach/suggest all the claimed features of claim 1 above, where Tang, and Sharma further teach/suggest the method comprising wherein the selection of the transmission interface is determined based on an intended destination of the packet (Tang, Fig. 3-6; Fig. 6-8; [0003]-[0009]; [0026]-[0030]; [0034]; [0050]-[0051]; [0057]-[0063]; [0069]-[0080]; [0090]; and Sharma, Fig. 1; Fig. 3; Fig. 5; [0008]; [0014]; [0072]; [0110]-[0122]; [0167]). As per claim 18, Tang, Sharma, and Gadi teach/suggest all the claimed features of claim 2 above, where Tang, Sharma, and Gadi further teach/suggest the method comprising wherein the exact match flow entry is a route associated with a destination that has a specific Internet Protocol (IP) address (Tang, Fig. 3-6; Fig. 6-8; [0003]-[0009]; [0026]-[0030]; [0034]; [0050]-[0051]; [0057]-[0063]; [0069]-[0080]; [0090]; Sharma, Fig. 1; Fig. 3; Fig. 5; [0008]; [0046]; [0072]; [0078]-[0079]; [0110]-[0122]; [0167]; and Gadi, Fig. 2; [0030]; [0037]-[0039]), wherein it would have been obvious to one of ordinary skilled in the art that the resulting combination of the references further teaches the above claimed features as data is proper communicated for processing. As per claim 19, Tang, Sharma, and Gadi teach/suggest all the claimed features of claim 2 above, where Tang, Sharma, and Gadi further teach/suggest the method comprising wherein the exact match flow entry has a subnet mask of 255.255.255.255 (Tang, Fig. 3-6; Fig. 6-8; [0003]-[0009]; [0026]-[0030]; [0034]; [0050]-[0051]; [0057]-[0063]; [0069]-[0080]; [0090]; Sharma, Fig. 1; Fig. 3; Fig. 5; [0008]; [0014]; [0046]; [0072]; [0078]-[0079]; [0110]-[0122]; [0167]; and Gadi, Fig. 2; [0030]; [0037]-[0039]), wherein it would have been obvious to one of ordinary skilled in the art that the resulting combination of the references further teaches the above claimed features as data is proper communicated for processing. As per claim 20, claim 20 is rejected in accordance to the same rational and reasoning as the above rejection of claim 1, wherein Tang teach/suggest a method comprising: operating with, using an application executing on a container in a pod on a physical host, a transmission interface associated with the pod over which to transmit a packet based on whether the packet is internal network traffic or external network traffic, wherein each pod on the physical host comprises transmission interface, the transmission interface comprising a virtual Ethernet interface, wherein the virtual Ethernet interface is for internal network traffic and internal network traffic is destined for another pod on the physical host, wherein internet network traffic is transmitted over the virtual Ethernet interface and processed by a host bridge, wherein external network traffic is destined for another pod on a different physical host, wherein external network traffic is transmitted accordingly, being processed by the host bridge, wherein the transmission interface is the virtual Ethernet interface; receiving the packet by the host bridge in the physical host, wherein the packet is destined for a second container on a second pod in executing on the physical host; and transmitting, by the host bridge, the packet to a second virtual Ethernet interface, wherein the second pod is associated with the second virtual Ethernet interface (Fig. 3-4; Fig. 6-8; [0003]-[0009]; [0026]-[0030]; [0034]; [0059]-[0063]; [0069]-[0080]; and [0090]). Tang does not teach the method comprising: selecting accordingly, comprising a set of transmission interfaces, the set of transmission interfaces comprising: a virtual function mapped to a data processing unit (DPU), executing using a processor on the physical host, wherein the virtual function is for external network traffic, being transmitted over the virtual function and is offloaded from the processor on the physical host to the DPU, wherein network traffic is processed either by one or the DPU. Sharma teaches/suggests a method comprising: selecting accordingly, comprising a set of transmission interfaces, the set of transmission interfaces comprising: a virtual function operating accordingly, executing using a processor on the physical host, wherein the virtual function is for external network traffic, being transmitted over the virtual function, wherein network traffic is processed either by one or another(Fig. 1; Fig. 3; Fig. 5; [0008]; [0014]; [0072]; [0110]-[0122]; and [0167]). Gadi teach/suggest a method comprising: being mapped to a data processing unit (DPU), being offloaded from the processor on the physical host to the DPU, being processed by the DPU (Fig. 2; [0030]; and [0037]-[0039]). It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Sharma’s interfacing architecture and Gadi’s DPU into Tang’s method for the benefit of simplifying the configuration and reconfiguration of virtual router (Sharma, [0012]) and offloading workload to the DPU (Gadi, [0030]) to obtain the invention as specified in claim 20. II. PERTINENT RELATED PRIOR ART Mariappan et al. (US Pub.: 2020/0314015):discloses a network controller selecting a virtual network interface from multiple available virtual network interfaces, usable by a logically-related group of one or more containers (“pod”) that is a member of the service, and configures the selected virtual network interface as the exposed interface for the backend to the service. III. CLOSING COMMENTS CONCLUSION STATUS OF CLAIMS IN THE APPLICATION The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i): CLAIMS REJECTED IN THE APPLICATION Per the instant office action, claims 1-20 have received a first action on the merits and are subject of a first action non-final. DIRECTION OF FUTURE CORRESPONDENCES Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHUN KUAN LEE whose telephone number is (571)272-0671. The examiner can normally be reached Monday-Friday. IMPORTANT NOTE If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached on (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHUN KUAN LEE/Primary Examiner Art Unit 2181 June 27, 2026
Read full office action

Prosecution Timeline

Show 4 earlier events
Jan 20, 2026
Response Filed
Jan 24, 2026
Examiner Interview Summary
Mar 12, 2026
Final Rejection mailed — §103
May 18, 2026
Interview Requested
Jun 10, 2026
Applicant Interview (Telephonic)
Jun 12, 2026
Request for Continued Examination
Jun 17, 2026
Response after Non-Final Action
Jul 01, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12665782
PROCESSING SYSTEM, RELATED INTEGRATED CIRCUIT, DEVICE AND METHOD
3y 4m to grant Granted Jun 23, 2026
Patent 12650941
METHOD AND RELATED APPARATUS FOR PCIE DATA TRANSMISSION
1y 8m to grant Granted Jun 09, 2026
Patent 12645195
METHOD FOR GENERATING A TWIN SENSOR BY WAY OF PARAMETER INHERITANCE
3y 3m to grant Granted Jun 02, 2026
Patent 12639235
CROSS-DOMAIN VOLTAGE BUS RESOURCE SHARING FOR IMPROVED POWER DELIVERY NETWORK
2y 9m to grant Granted May 26, 2026
Patent 12639237
MEMORY DEVICE WITH INTERNAL PROCESSING INTERFACE
1y 9m to grant Granted May 26, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

3-4
Expected OA Rounds
68%
Grant Probability
72%
With Interview (+3.8%)
3y 4m (~1y 3m remaining)
Median Time to Grant
High
PTA Risk
Based on 681 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month