Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 10-11, 17-18, 20-21 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Mosinskis et al. (WO 2007098073 and Mosinskis hereinafter.) in view of Lin et al. (TW I729887 B and Lin hereinafter.).
Regarding claim 1, Mosinskis discloses a device [fig. 10] comprising: a comparator circuit [differential control circuit 20 and current source I2], responsive to a current [I2], that is configured to receive an input signal and [signal INP] a reference signal [signal INN], to compare the input signal with the reference signal [variable and differing currents through FETS of 26 caused by INP and INN], and to generate an output signal [output node between a first ZL and FET accepting INP signal wherein output node is coupled to a gate terminal of a first FET of 28] that indicates the result of comparison; and a current generator circuit [I2]. Mosinskis does not explicitly disclose the current generator circuit including: a first current mirror circuit configured to generate the current; and a current booster circuit configured to amplify the current from an initial current value to a higher current value and to maintain the current at the higher current value over a predetermined duration of time, wherein the current booster circuit is connected in parallel with a transistor of the current mirror circuit.
However, Lin discloses the current generator circuit [fig. 3, current mirror circuit 310] including: a first current mirror circuit [T41 , T43 with T42] configured to generate the current [Iload when T42 is active]; and a current booster circuit [T44, T45 and AN31] configured to amplify the current from an initial current value to a higher current value and to maintain the current at the higher current value over a predetermined duration of time [as shown in fig. 4], wherein the current booster circuit is connected in parallel with a transistor of the current mirror circuit [T44 and T45 in parallel with T42 and T43]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Mosinskis to include the current generator circuit including: a first current mirror circuit configured to generate the current; and a current booster circuit configured to amplify the current from an initial current value to a higher current value and to maintain the current at the higher current value over a predetermined duration of time wherein the current booster circuit is connected in parallel with a transistor of the current mirror circuit as taught by Lin to improve robustness of a circuit
Regarding claim 2, Mosinskis in view of Lin discloses further wherein: the first current mirror circuit includes: a first transistor [Lin, T41] configured to generate a transistor current therethrough; and a second transistor [Lin, T43] configured to mirror the transistor current; and the current booster circuit includes a third transistor [Lin, T44] and a fourth transistor [Lin, T45] connected in series with the third transistor [Lin, T44 in series with T45], a source drain terminal of the third transistor is connected to a source/drain terminal of the second transistor [Lin, T44 coupled to T43], and a source/drain terminal of the fourth transistor is connected to the other source/drain terminal of the second transistor [Lin, T45 coupled to T43].
Regarding claim 3, Mosinskis in view of Lin discloses further comprising a current source circuit [Lin, unlabeled circuitry driving IREF into T41] configured to generate a substantially constant current and connected in series with the first transistor [as shown], wherein the series connection of the first transistor and the current source circuit is connected across a first supply voltage [Lin, VDD2] and a second supply voltage or electrical ground [Lin, GND].
Regarding claim 4, Mosinskis in view of Lin discloses further wherein: the first transistor is connected between the first supply voltage and the current source circuit [as shown]; and the current source circuit is connected between the first transistor and the second supply voltage or electrical ground [as shown].
Regarding claim 5, Mosinskis in view of Lin discloses further wherein: the current source circuit is connected between the first supply voltage and the first transistor [as shown]; and the first transistor is connected between the current source circuit and the second supply voltage or electrical ground [as shown].
Regarding claim 10, Mosinskis discloses a device [fig. 10] comprising: a first comparator circuit [differential control circuit 20 and current source I2], responsive to a first current [I2], that is configured to receive an input signal [INP] and a reference signal [INN], to compare the input signal with the reference signal [variable and differing currents through FETS of 26 caused by INP and INN], and to generate a first output signal that corresponds to the input signal [output node between a first ZL and FET accepting INP signal wherein output node is coupled to a gate terminal of a first FET of 28] and a second output signal that corresponds to the reference signal [output node between a second ZL and FET accepting INN signal wherein output node is coupled to a gate terminal of a second FET of 28]; a first current generator circuit [I2]. Mosinskis discloses further a second comparator circuit [28 and 18], responsive to a second current [current through 18], that is configured to receive the first and second output signals [as shown], to compare the first output signal with the second output signal [variable and differing currents through FETS of 28 caused by signals on associated gates of FETS within 28], and to generate a third output signal that indicates the result of comparison [output of 28 onto inverting input of 22]; and a second current generator circuit including: a second current mirror circuit [14 and 18] configured to generate the second current [iOut]. Mosinskis does not explicitly disclose the first current generator circuit including a first current mirror circuit configured to generate the first current; and a first current booster circuit configured to amplify the first current from a first initial current value to a first higher current value and to maintain the first current at the first higher current value over a predetermined duration of time; a second current booster circuit configured to amplify the second current from a second initial current value to a second higher current value and to maintain the second current at the second higher current value over the predetermined duration of time, wherein the first current booster circuit is connected in parallel with a transistor of the first current mirror circuit.
However, Lin discloses the first current generator circuit [fig. 3, current mirror circuit 310] including a first current mirror circuit [T41 , T43 with T42] configured to generate the first current [Iload when T42 is active]; and a first current booster circuit [a first current mirror circuit 310] configured to amplify the first current [a first iload wherein the first iload is associated with the first comparator circuit of Mosinskis] from a first initial current value to a first higher current value and to maintain the first current at the first higher current value over a predetermined duration of time [as shown in fig. 4]; a second current booster circuit [a second current mirror circuit 310] configured to amplify the second current [a second iload wherein the second iload is associated with the second comparator circuit of Mosinskis] from a second initial current value to a second higher current value and to maintain the second current at the second higher current value over the predetermined duration of time [as shown in fig. 4], wherein the first current booster circuit is connected in parallel with a transistor of the first current mirror circuit [T44 and T45 in parallel with T42 and T43]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Mosinskis to include the first current generator circuit including a first current mirror circuit configured to generate the first current; and a first current booster circuit configured to amplify the first current from a first initial current value to a first higher current value and to maintain the first current at the first higher current value over a predetermined duration of time; a second current booster circuit configured to amplify the second current from a second initial current value to a second higher current value and to maintain the second current at the second higher current value over the predetermined duration of time, wherein the first current booster circuit is connected in parallel with a transistor of the first current mirror circuit as taught by Lin to improve robustness of a circuit
Regarding claim 11, Mosinskis in view of Lin discloses further wherein: the first current mirror circuit includes: a first transistor [Lin, T41] configured to generate a transistor current therethrough; and a second transistor [Lin, T43] configured to mirror the transistor current; and the first current booster circuit includes a third transistor [Lin, T46] and a fourth transistor [Lin, T47] connected in series with the third transistor, wherein the third and fourth transistors are connected in parallel with the second transistor [as shown].
Regarding claim 17, Mosinskis discloses [fig. 10] a method comprising: receiving an input signal [signal INP] and a reference signal [signal INN]; in response to a current provided by a current mirror circuit [28 effecting 24 onto 26], comparing the input signal with the reference signal; generating an output signal that indicates the result of comparison [output node between a first ZL and FET accepting INP signal wherein output node is coupled to a gate terminal of a first FET of 28]. Mosinskis does not explicitly disclose amplifying the current from an initial current value to a higher current value; and maintaining the current at the higher current value over a predetermined duration of time.
However, Lin discloses amplifying the current from an initial current value to a higher current value; and maintaining the current at the higher current value over a predetermined duration of time [as shown in fig. 4].
Regarding claim 18, further comprising: wherein providing the current comprises: generating, by a first transistor of the current mirror circuit [Lin, T41], a transistor current [iload]; mirroring, by a second transistor [Lin, T43] of the current mirror circuit, the transistor current; and wherein amplifying [via T44 and T45] the current comprises: in response to a settling signal [Lin, signals CNT], connecting a series connection of third [Lin, T43] and fourth [Lin, T44] transistors in parallel with the second transistor [as shown].
Regarding claim 20, Mosinskis in view of Lin discloses [Lin, fig. 3 and 4] wherein providing the current comprises: generating, by a first transistor of the current mirror circuit [Lin, T41], a transistor current; generating, by a current source [IREF] circuit connected in series with the first transistor, a current having a substantially constant current value [IREF is a reference current]; and mirroring, by a second transistor [Lin, T45 allowing mirroring of T45] of the current mirror circuit, the transistor current [as shown].
Regarding claim 21, Mosinskis in view of Lin discloses further wherein a gate terminal of the fourth transistor is configured to receive a settling voltage signal to amplify the current [Lin, T45 accepting signal CNT].
Regarding claim 23, Mosinskis in view of Lin discloses further wherein a gate terminal of the fourth transistor is configured to receive the settling signal to amplify the current [Lin, T44 accepting signal CNT].
Claims 6-8, 13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Mosinskis in view of Lin further in view of Kim et al. (KR 0167709 B1 and Kim hereinafter.)
Regarding claim 6, Mosinskis in view of Lin discloses all the features regarding claim 1 as indicated above. Mosinskis in view of Lin does not explicitly disclose further comprising a second current mirror circuit, wherein the comparator circuit is connected between the first and second current mirror circuits.
However, Kim discloses [fig. 1] further comprising a second current mirror circuit [10], wherein the comparator circuit [20 and associated circuitry] is connected between the first [40] and second current mirror circuits [as shown]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Mosinskis in view of Lin to include a second current mirror circuit, wherein the comparator circuit is connected between the first and second current mirror circuits as taught by Kim to improve hysteresis within a comparator.
Regarding claim 7, Mosinskis in view of Lin further in view of Kim discloses further wherein :the first current mirror circuit is connected between a first supply voltage and the comparator circuit [first current mirror circuit of Lin directly coupled to ground and comparator circuit of Mosinskis directly coupled to VDD]; and the second current mirror circuit is connected between a second supply voltage or electrical ground and the comparator circuit [20 coupled between VCC and ground].
Regarding claim 8, Mosinskis in view of Lin further in view of Kim discloses further wherein the first current mirror circuit is connected between a second supply voltage or electrical ground and the comparator circuit [first current mirror circuit of Lin directly coupled to ground and comparator circuit of Mosinskis directly coupled to VDD the second current mirror circuit [10] is connected between a first supply voltage and the comparator circuit [20 coupled between VCC and ground]
Regarding claim 13, Mosinskis in view of Lin discloses all the features regarding claim 10 as indicated above. Mosinskis in view of Lin discloses further wherein the second current mirror circuit [Mosinskis, 14 and 18] is connected between a first supply voltage [Mosinskis, ground] and the second comparator circuit [as shown]. Mosinskis in view of Lin does not explicitly disclose wherein the device further comprising a third current mirror circuit connected between the second comparator circuit and a second supply voltage or electrical ground.
However, Kim discloses [fig. 1] wherein the device further comprising a third current mirror circuit [10] connected between the second comparator circuit [20] and a second supply voltage or electrical ground [ground]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Mosinskis in view of Lin to include the device further comprising a third current mirror circuit connected between the second comparator circuit and a second supply voltage or electrical ground as taught by Kim to improve hysteresis within a comparator
Regarding claim 15, Mosinskis in view of Lin discloses all the features regarding claim 10 as indicated above. Mosinskis in view of Lin discloses further wherein the second current mirror circuit [Lin, 310] is connected between the second comparator circuit [Mosinskis, 28] and a second supply voltage or electrical ground [as shown]. Mosinskis in view of Lin does not explicitly disclose further comprising a third current mirror circuit connected between a first supply voltage [VCC] and the second comparator circuit.
However, Kim discloses [fig. 1] further comprising a third current mirror circuit [10] connected between a first supply voltage [VCC] and the second comparator circuit [20]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Mosinskis in view of Lin to include a third current mirror circuit connected between a first supply voltage [VCC] and the second comparator circuit as taught by Kim to improve hysteresis within a comparator.
Claims 12 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Mosinskis in view of Lin further in view of Hong et al. (KR 20210151399 A and Hong hereinafter.).
Regarding claim 12, Mosinskis in view of Lin discloses all the features regarding claim 10 as indicated above. Mosinskis in view of Lin discloses further wherein the first current mirror circuit [Lin, T41 and T43] is connected between the first comparator circuit [first comparator circuit of Mosinskis] and a second supply voltage or electrical ground [Mosinskis, differential control circuit 20 and current source I2 coupled to between highrail and ground]. Mosinskis in view of Lin does not explicitly disclose further comprising a third current mirror circuit connected between a first supply voltage and the first comparator circuit, wherein the first current mirror circuit is connected between the first comparator circuit and a second supply voltage or electrical ground.
However, Hong discloses [fig. 3] further comprising a third current mirror circuit [511 and 513] connected between a first supply voltage [VDD] and the first comparator circuit [512 and 514]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Mosinskis in view of Lin to include a third current mirror circuit connected between a first supply voltage and the first comparator circuit, wherein the first current mirror circuit is connected between the first comparator circuit and a second supply voltage or electrical ground as taught by Hong to improve timing performance in a circuit.
Regarding claim 22, Mosinskis in view of Lin further in view of Hong discloses further wherein the third current mirror includes a fifth transistor [Hong, 511] and a sixth transistor [Hong, 513], gate terminals of the fifth and sixth transistors are connected to each other and to a source/drain terminal of the fifth transistor [as shown].
Allowable Subject Matter
Claim 14 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Applicant’s arguments with respect to claim(s) claims 1-2 and 10, 17-18 and 20 have been considered but are moot because the new ground of rejection. Regarding claims 1-2 and 10, 17-18 and 20 a new ground(s) of rejection is made with Mosinskis in view of Lin as set forth above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES G YEAMAN whose telephone number is (571)272-5580. The examiner can normally be reached Mon - Fri 954 Schedule.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Taelor Kim can be reached at (571) 270-7166. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAMES G YEAMAN/ Examiner, Art Unit 2836
/REGIS J BETSCH/ SPE, Art Unit 2836
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