DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Information Disclosure Statement
The Information Disclosure Statements (IDS) submitted on July 22, 2024 and March 5, 2026 have been considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-7 and 12-14 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 10,706,952 B1 to Steven Lee Gregor, et al. (hereafter Gregor).
Regarding Independent Claim 1, Gregor discloses an integrated circuit, comprising:
a memory having an array (A memory cell array: Gregor, col.6:32); and
a memory BIST (MBIST) controller (A MBIST diagnostics system: Gregor, col.5:65),
the MBIST controller configured to perform memory testing runs on the memory (The MBIST system performing a memory test: Gregor, col.6:39-40),
the MBIST controller having:
a first counter configured to count uncorrectable errors during each memory testing run (Monitoring how many error indications are raised: Gregor, col.7:42-45); and
a repair control circuit configured to,
in response to an error found during a memory testing run (Encountering correctable errors: Gregory, col.7:42-45),
determine whether at least one of row repair or column repair can be applied to repair the error (Repairing soft errors using ECC logic: Gregory, col.8:21-26).
Regarding Claim 2, Gregor discloses the integrated circuit of claim 1, wherein
each counted uncorrectable error corresponds to a multi-bit error (An uncorrectable error being a corruption of multiple bits: Gregor, col.5:15-17)
detected within an accessed data element returned to the MBIST controller as read test data from the array (The tested data being that returned and compared to an expected sample: Gregor, col.4:22-28).
Regarding Claim 3, Gregor discloses the integrated circuit of claim 2, wherein
the MBIST controller further comprises a multi-bit fault detection flag (Outputting an Uncorrectable Error indicator: Gregor, col.5:15-18),
wherein the MBIST controller is configured to assert the multi-bit fault detection flag in response to occurrence of at least one multi-bit error (Signaling on the Uncorrectable Error indication in response to identifying an uncorrectable error: Gregor, col.5:15-18).
Regarding Claim 4, Gregor discloses the integrated circuit of claim 3, wherein the MBIST controller further comprises:
a second counter configured to count errors found within accessed data elements returned to the MBIST controller as read data from the array during each memory testing run (A secondary counter in the accumulator 180: Gregor, col.7:30-32),
wherein each counted error by the second counter may correspond to either a single bit error in a corresponding accessed data element or a multi-bit error in the corresponding accessed data element (Where the error count includes both correctable and uncorrectable errors: Gregor, col.7:33-35).
Regarding Claim 5, Gregor discloses the integrated circuit of claim 1, wherein each memory testing run comprises
a set of writes to write corresponding test data to the array (Writing information in the memory cell array: Gregor, col.1:20-21),
a set of reads to obtain corresponding read data from the array (Reading information from the array: Gregor, col.1:22), and
comparisons between the obtained read data and expected read data to detect occurrence of any bit errors (Comparing the read data to the intended written data to identify errors: Gregor, col.1:23).
Regarding Claim 6, Gregor discloses the integrated circuit of claim 5, wherein
when multiple bit errors are detected within read test data returned in response to a same access address of read access request (An uncorrectable error being multiple bit errors: Gregor, col.5:15-18),
the MBIST controller is configured to update the first counter to count the multiple bit errors as an uncorrectable error (Updating a first indicator for an uncorrectable error: Gregor, col.5:17-18; An indicator inherently provides a limited count ability ranging from 0-1).
Regarding Claim 7, Gregor discloses the integrated circuit of claim 6, wherein
the MBIST controller is configured to only update the first counter once for any multiple bit error corresponding to the same access address (Updating the indicator once on encountering a multiple bit error: Gregor, col.5:17-18; An indicator necessarily cannot count past 1).
Regarding Claim 12, Gregor discloses the integrated circuit of claim 1, wherein,
after completion of a set of memory testing runs (Performing a functional operation test: Gregor, col.7:9-11),
the memory is identified as a bad part (Reporting an excess number of errors to the user: Gregor, col.7:46-49) in response to the count of uncorrectable errors in the first counter being greater than a predetermined threshold (The report being made in response to the number of errors exceeding a predetermined threshold: Gregor, col.7:37-39).
Regarding Claim 13, Gregor discloses the integrated circuit of claim 1, further comprising
a plurality of memories (Multiple memories 150: Gregor, Figure 1), wherein, for each memory testing run, the MBIST controller is configured to perform the memory testing run on all memories of the plurality of memories (Performing memory test checks on all memories: Gregor, col.6:21-24).
Regarding Claim 14, Gregor discloses the integrated circuit of claim 13, wherein
the MBIST controller is configured to reset the first counter prior to each memory testing run (Resetting key indicators are inherent in a repeat test),
such that, after completion of each memory testing run (Completing a test run: Gregor, col.7:8-10),
the first counter is configured to provide the count of uncorrectable errors which collectively occurred in all the memories of the plurality of memories during the memory testing run (Returning the error count of the MBIST run, which includes all memory arrays: Gregor, col.7:30-34).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 8-11 and 15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 10,706,952 B1 to Steven Lee Gregor, et al. (hereafter Gregor) in view of US 2004/0246796 A1 to Haluk Konuk, et al. (hereafter Konuk).
Regarding Claim 8, Gregor discloses using ECC logic to correct correctable errors, but does not disclose using a row or column repair (Gregor, col.8:21-25). Konuk, on the other hand, discloses an integrated circuit as in claim 5, wherein
the repair control circuit (Row repair circuit 36: Konuk, ¶[0025]) is configured to,
upon completion of a first memory testing run (In response to identifying a defect: Konuk, ¶[0028]),
determine whether a row/column repair can be applied to repair a first detected bit error (Identify if a row repair would appropriately fix the defect: Konuk, ¶[0037])).
Konuk teaches that iteratively testing memory matrices, implementing row/column fixes, guarantees finding a repair solution, if one exists, and can do so more rapidly than by implementing an exhaustive analysis (Konuk, ¶[0044]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the iterative testing/repair method of Konuk with the testing algorithm of Gregor, with a reasonable expectation of success. Both inventions are well known in the field of MBIST systems and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 9, Konuk discloses the integrated circuit of claim 8, wherein,
the repair control circuit (Row repair circuit 36: Konuk, ¶[0025]) is configured to,
in response to determining that row/column repair can be applied to repair the first detected bit error (In response to identifying a defect: Konuk, ¶[0028]),
configure a repair control register for the first detected bit error (Repairing using a redundant row to bypass the defect: Konuk, ¶[0029]).
Regarding Claim 10, Konuk discloses the integrated circuit of claim 9, wherein:
for a second memory testing run (Iteratively running the error check: Konuk, ¶[0042]), the MBIST controller is configured to reset the first counter such that, during the second memory testing run, the repair is applied to the first detected bit error (Applying a first error solution using either a redundant row or redundant column and then rerunning the check: Konuk, ¶[0042]), and
upon completion of the second memory testing run, the repair control circuit is configured to determine whether row/column repair can be applied to repair a second detected bit error (Rerunning the defect analysis to repair additional errors: Konuk, ¶[0042])
which is in a different location of the array as the first detected bit error (Subsequent defect resolutions following a first defect solution will inherently resolves defects in different locations from the first).
Regarding Claim 11, Konuk discloses the integrated circuit of claim 10, wherein
the repair control circuit is configured to apply row repair for the first detected bit error and apply column repair to the second detected bit error (Applying a first defect resolution followed by a second defect resolution, including combinations of rows and columns, which necessarily includes the species of ‘Row First, Column Second’: Konuk, ¶[0069]).
Regarding Independent Claim 15, Gregor discloses an integrated circuit, comprising:
a memory having an array (A memory cell array: Gregor, col.6:32); and
a memory BIST (MBIST) controller (A MBIST diagnostics system: Gregor, col.5:65),
the MBIST controller configured to perform memory testing runs on the memory (The MBIST system performing a memory test: Gregor, col.6:39-40),
each memory testing run including a set of writes to write corresponding test data to the array (Writing information in the memory cell array: Gregor, col.1:20-21),
a set of reads to obtain corresponding read data from the array (Reading information from the array: Gregor, col.1:22), and
comparisons between the obtained read data and expected read data to detect occurrences of any hit errors (Comparing the read data to the intended written data to identify errors: Gregor, col.1:23),
the MBIST controller having
a first counter configured to count uncorrectable errors during each memory testing run (A first uncorrectable error indicator: Gregor, col.5:15-18).
Gregor teaches the architecture and testing algorithm for a MBIST system and discloses performing error corrections based on ECC codes (Gregor, col.8:21-25) but does not explicitly teach row and column repair registers, configured to apply a column repair to repair a first detected bit error, a second memory testing run performed while applying column repair to the first detected bit error, and applying a row repair to a second detected bit error. Konuk, however, discloses a MBIST controller, including:
the MBIST controller having
a row repair control register (A row repair circuit 36: Konuk, ¶[0025]),
a column repair control register (A column repair circuit 38: Konuk, ¶[0025]),
the MBIST controller configured to:
upon completion of a first memory testing run (Iteratively running the error check: Konuk, ¶[0042]),
configure the column repair control register to apply column repair to repair a first detected bit error (Column repair circuit 38 implementing a column repair: Konuk, ¶[0030]);
reset the first counter prior to commencing a second memory testing run (Resetting key indicators are inherent in a repeat test),
the second memory testing run is performed while applying column repair to repair the first detected bit error (Iteratively running the error check with the solution implemented: Konuk, ¶[0042]); and
upon completion of a second memory testing run, configure the row repair control register to apply row repair to repair a second detected bit error (Applying a first defect resolution followed by a second defect resolution, including combinations of rows and columns, which necessarily includes the species of ‘Column First, Row Second’: Konuk, ¶[0069]).
Konuk teaches that iteratively testing memory matrices, implementing row/column fixes, guarantees finding a repair solution, if one exists, and can do so more rapidly than by implementing an exhaustive analysis (Konuk, ¶[0044]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the iterative testing/repair method of Konuk with the testing algorithm of Gregor, with a reasonable expectation of success. Both inventions are well known in the field of MBIST systems and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 16, Gregor discloses the integrated circuit of claim 15, wherein
when multiple bit errors are detected within read test data returned in response to a same access address of read access request (An uncorrectable error being multiple bit errors: Gregor, col.5:15-18),
the MBIST controller is configured to update the first counter to count the multiple bit errors as an uncorrectable error (Updating a first indicator for an uncorrectable error: Gregor, col.5:17-18; An indicator inherently provides a limited count ability ranging from 0-1).
Regarding Claim 17, Gregor discloses the integrated circuit of claim 16, wherein
the MBIST controller further comprises a multi-bit fault detection flag (Outputting an Uncorrectable Error indicator: Gregor, col.5:15-18),
wherein the MBIST controller is configured to assert the multi-bit fault detection flag in response to occurrence of at least one multi-bit error (Signaling on the Uncorrectable Error indication in response to identifying an uncorrectable error: Gregor, col.5:15-18).
Regarding Claim 18, Gregor discloses the integrated circuit of claim 16, wherein
the MBIST controller is configured to only update the first counter once for any multiple bit error corresponding to the same access address (Updating the indicator once on encountering a multiple bit error: Gregor, col.5:17-18; An indicator necessarily cannot count past 1).
Regarding Claim 19, Gregor discloses the integrated circuit of claim 15, wherein,
after completion of a set of memory testing runs (Performing a functional operation test: Gregor, col.7:9-11),
the memory is identified as a bad part (Reporting an excess number of errors to the user: Gregor, col.7:46-49) in response to the count of uncorrectable errors in the first counter being greater than a predetermined threshold (The report being made in response to the number of errors exceeding a predetermined threshold: Gregor, col.7:37-39).
Regarding Claim 20, Konuk discloses the integrated circuit of claim 15, wherein
the memory further comprises a set of redundant columns and a set of redundant rows (Memory including one or more redundant rows and/or columns: Konuk, ¶[0024]), and
the MBIST controller (A controller: Konuk, ¶[0023]) further comprises a repair control circuit configured to:
configure the column and row repair control registers (Column and row repair control circuits: Konuk, ¶[0025]),
when the repair control register is configured for the row repair, apply the row repair during a memory testing run (Applying a row repair solution when configured for a row repair: Konuk, ¶[0028-0029]), and
when the column control register is configured for the column repair, apply the column repair during the memory testing run (Applying a column repair solution when configured for column repair: Konuk, ¶[0030]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2002/0108073 A1 to Brian William Hughes: Teaching a MBIST system effectuating repairs first by columns and then by rows.
US 2026/0024606 A1 to Chen He, et al.: Teaching a partition BIST controller configured to store a failure indicator for both correctable and uncorrectable failures.
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/CHRISTOPHER LANE REECE/Examiner, Art Unit 2824
/DOUGLAS KING/Primary Examiner, Art Unit 2824