DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Response to Amendment
The amendment filed June 22, 2026 has been entered. Claims 1-20 remain pending in this application. Claims 1-2, 5 and 15 have been amended. No claims have been added. No new matter has been added.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 10,706,952 B1 to Steven Lee Gregor, et al. (hereafter Gregor) in view of US 2004/0246796 A1 to Haluk Konuk, et al. (hereafter Konuk).
Regarding Amended Independent Claim 1, Gregor discloses an integrated circuit, comprising:
a memory having an array (A memory cell array: Gregor, col.6:32); and
a memory BIST (MBIST) controller (A MBIST diagnostics system: Gregor, col.5:65),
the MBIST controller configured to perform memory testing runs on the memory (The MBIST system performing a memory test: Gregor, col.6:39-40)
without applying ECC (Running a memory test without applying ECC: Gregor, col.3:22-28),
the MBIST controller having:
a first counter configured to count uncorrectable errors during each memory testing run (Monitoring how many error indications are raised: Gregor, col.7:42-45; The number of uncorrectable errors: Gregor, col.7:32-35); and
a repair control circuit configured to,
in response to an error found during a memory testing run (Encountering correctable errors: Gregory, col.7:42-45),
determine whether at least one of row repair or column repair can be applied to repair the error (Repairing soft errors using ECC logic: Gregory, col.8:21-26).
Gregor does not expressly disclose a testing scenario wherein row repair is applied by using at least one redundant row and column repair is applied by using at least one redundant column. Konuk, on the other hand, discloses a MBIST testing process including:
wherein row repair is applied by using at least one redundant row (Performing row repair by replacing a row with a redundant row: Konuk, ¶[0028]) and
column repair is applied by using at least one redundant column (Performing column repair by replacing a column with a redundant column: Konuk, ¶[0030]).
Konuk teaches that iteratively testing memory matrices, implementing row/column fixes, guarantees finding a repair solution, if one exists, and can do so more rapidly than by implementing an exhaustive analysis (Konuk, ¶[0044]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the iterative testing/repair method of Konuk with the testing algorithm of Gregor, with a reasonable expectation of success. Both inventions are well known in the field of MBIST systems and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Amended Claim 2, Gregor discloses the integrated circuit of claim 1, wherein
each counted uncorrectable error corresponds to a multi-bit error (An uncorrectable error being a corruption of multiple bits: Gregor, col.5:15-17)
detected within an accessed data element returned to the MBIST controller as read test data from the array (The tested data being that returned and compared to an expected sample: Gregor, col.4:22-28),
wherein ECC is not performed on the read test data (Performing a physical view test of memory, wherein the logical module multiplexers, responsible for ECC, remain deactivated: Gregor, col.5:39-45).
Regarding Claim 3, Gregor discloses the integrated circuit of claim 2, wherein
the MBIST controller further comprises a multi-bit fault detection flag (Outputting an Uncorrectable Error indicator: Gregor, col.5:15-18),
wherein the MBIST controller is configured to assert the multi-bit fault detection flag in response to occurrence of at least one multi-bit error (Signaling on the Uncorrectable Error indication in response to identifying an uncorrectable error: Gregor, col.5:15-18).
Regarding Claim 4, Gregor discloses the integrated circuit of claim 3, wherein the MBIST controller further comprises:
a second counter configured to count errors found within accessed data elements returned to the MBIST controller as read data from the array during each memory testing run (A secondary counter in the accumulator 180: Gregor, col.7:30-32),
wherein each counted error by the second counter may correspond to either a single bit error in a corresponding accessed data element or a multi-bit error in the corresponding accessed data element (Where the error count includes both correctable and uncorrectable errors: Gregor, col.7:33-35).
Regarding Amended Claim 5, Gregor discloses the integrated circuit of claim 1, wherein each memory testing run comprises
a set of writes to write corresponding test data to the array (Writing information in the memory cell array: Gregor, col.1:20-21),
a set of reads to obtain corresponding read data from the array (Reading information from the array: Gregor, col.1:22),
in which ECC is not performed on the obtained read data (Performing a physical view test of memory, wherein the logical module multiplexers, responsible for ECC, remain deactivated: Gregor, col.5:39-45), and
comparisons between the obtained read data and expected read data to detect occurrence of any bit errors (Comparing the read data to the intended written data to identify errors: Gregor, col.1:23).
Regarding Claim 6, Gregor discloses the integrated circuit of claim 5, wherein
when multiple bit errors are detected within read test data returned in response to a same access address of read access request (An uncorrectable error being multiple bit errors: Gregor, col.5:15-18),
the MBIST controller is configured to update the first counter to count the multiple bit errors as an uncorrectable error (Counting uncorrectable errors: Gregor, col.7:32-35).
Regarding Claim 7, Gregor discloses the integrated circuit of claim 6, wherein
the MBIST controller is configured to only update the first counter once for any multiple bit error corresponding to the same access address (Updating the indicator once on encountering a multiple bit error: Gregor, col.5:17-18; An indicator necessarily cannot count past 1).
Regarding Claim 8, Gregor discloses using ECC logic to correct correctable errors, but does not disclose using a row or column repair. Konuk, on the other hand, discloses an integrated circuit as in claim 5, wherein
the repair control circuit (Row repair circuit 36: Konuk, ¶[0025]) is configured to,
upon completion of a first memory testing run (In response to identifying a defect: Konuk, ¶[0028]),
determine whether a row/column repair can be applied to repair a first detected bit error (Identify if a row repair would appropriately fix the defect: Konuk, ¶[0037])).
Regarding Claim 9, Konuk discloses the integrated circuit of claim 8, wherein,
the repair control circuit (Row repair circuit 36: Konuk, ¶[0025]) is configured to,
in response to determining that row/column repair can be applied to repair the first detected bit error (In response to identifying a defect: Konuk, ¶[0028]),
configure a repair control register for the first detected bit error (Repairing using a redundant row to bypass the defect: Konuk, ¶[0029]).
Regarding Claim 10, Konuk discloses the integrated circuit of claim 9, wherein:
for a second memory testing run (Iteratively running the error check: Konuk, ¶[0042]), the MBIST controller is configured to reset the first counter such that, during the second memory testing run, the repair is applied to the first detected bit error (Applying a first error solution using either a redundant row or redundant column and then rerunning the check: Konuk, ¶[0042]), and
upon completion of the second memory testing run, the repair control circuit is configured to determine whether row/column repair can be applied to repair a second detected bit error (Rerunning the defect analysis to repair additional errors: Konuk, ¶[0042])
which is in a different location of the array as the first detected bit error (Subsequent defect resolutions following a first defect solution will inherently resolves defects in different locations from the first).
Regarding Claim 11, Konuk discloses the integrated circuit of claim 10, wherein
the repair control circuit is configured to apply row repair for the first detected bit error and apply column repair to the second detected bit error (Applying a first defect resolution followed by a second defect resolution, including combinations of rows and columns, which necessarily includes the species of ‘Row First, Column Second’: Konuk, ¶[0069]).
Regarding Claim 12, Gregor discloses the integrated circuit of claim 1, wherein,
after completion of a set of memory testing runs (Performing a functional operation test: Gregor, col.7:9-11),
the memory is identified as a bad part (Reporting an excess number of errors to the user: Gregor, col.7:46-49) in response to the count of uncorrectable errors in the first counter being greater than a predetermined threshold (The report being made in response to the number of errors exceeding a predetermined threshold: Gregor, col.7:37-39).
Regarding Claim 13, Gregor discloses the integrated circuit of claim 1, further comprising
a plurality of memories (Multiple memories 150: Gregor, Figure 1), wherein, for each memory testing run, the MBIST controller is configured to perform the memory testing run on all memories of the plurality of memories (Performing memory test checks on all memories: Gregor, col.6:21-24).
Regarding Claim 14, Gregor discloses the integrated circuit of claim 13, wherein
the MBIST controller is configured to reset the first counter prior to each memory testing run (Resetting key indicators are inherent in a repeat test),
such that, after completion of each memory testing run (Completing a test run: Gregor, col.7:8-10),
the first counter is configured to provide the count of uncorrectable errors which collectively occurred in all the memories of the plurality of memories during the memory testing run (Returning the error count of the MBIST run, which includes all memory arrays: Gregor, col.7:30-34).
Regarding Amended Independent Claim 15, Gregor discloses an integrated circuit, comprising:
a memory having an array (A memory cell array: Gregor, col.6:32); and
a memory BIST (MBIST) controller (A MBIST diagnostics system: Gregor, col.5:65),
the MBIST controller configured to perform memory testing runs on the memory (The MBIST system performing a memory test: Gregor, col.6:39-40),
each memory testing run including a set of writes to write corresponding test data to the array (Writing information in the memory cell array: Gregor, col.1:20-21),
a set of reads to obtain corresponding read data from the array (Reading information from the array: Gregor, col.1:22), and
comparisons between the obtained read data and expected read data to detect occurrences of any bit errors (Comparing the read data to the intended written data to identify errors: Gregor, col.1:23),
wherein ECC is not performed on any of the obtained corresponding read data from the array (Running a memory test without applying ECC: Gregor, col.3:22-28),
the MBIST controller having
a first counter configured to count uncorrectable errors during each memory testing run (A first uncorrectable error indicator: Gregor, col.5:15-18; The number of uncorrectable errors: Gregor, col.7:32-35).
Gregor does not disclose the MBIST controller having a row repair control register, a column repair control register, the MBIST controller configured to: upon completion of a first memory testing run, configure the column repair control register to apply column repair to repair a first detected bit error; reset the first counter prior to commencing a second memory testing run, the second memory testing run is performed while applying column repair to repair the first detected bit error; and upon completion of a second memory testing run, configure the row repair control register to apply row repair to repair a second detected bit error.
Konuk, however, discloses a MBIST controller including:
a row repair control register (A row repair circuit 36: Konuk, ¶[0025]),
a column repair control register (A column repair circuit 38: Konuk, ¶[0025]), and
the MBIST controller configured to:
upon completion of a first memory testing run (Iteratively running the error check: Konuk, ¶[0042]),
configure the column repair control register to apply column repair to repair a first detected bit error (Column repair circuit 38 implementing a column repair: Konuk, ¶[0030]);
reset the first counter prior to commencing a second memory testing run (Resetting key indicators are inherent in a repeat test),
the second memory testing run is performed while applying column repair to repair the first detected bit error (Iteratively running the error check with the solution implemented: Konuk, ¶[0042]); and
upon completion of a second memory testing run, configure the row repair control register to apply row repair to repair a second detected bit error (Applying a first defect resolution followed by a second defect resolution, including combinations of rows and columns, which necessarily includes the species of ‘Column First, Row Second’: Konuk, ¶[0069]).
Konuk teaches that iteratively testing memory matrices, implementing row/column fixes, guarantees finding a repair solution, if one exists, and can do so more rapidly than by implementing an exhaustive analysis (Konuk, ¶[0044]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the iterative testing/repair method of Konuk with the testing algorithm of Gregor, with a reasonable expectation of success. Both inventions are well known in the field of MBIST systems and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 16, Gregor discloses the integrated circuit of claim 15, wherein
when multiple bit errors are detected within read test data returned in response to a same access address of read access request (An uncorrectable error being multiple bit errors: Gregor, col.5:15-18),
the MBIST controller is configured to update the first counter to count the multiple bit errors as an uncorrectable error (Counting uncorrectable errors: Gregor, col.7:32-35).
Regarding Claim 17, Gregor discloses the integrated circuit of claim 16, wherein
the MBIST controller further comprises a multi-bit fault detection flag (Outputting an Uncorrectable Error indicator: Gregor, col.5:15-18),
wherein the MBIST controller is configured to assert the multi-bit fault detection flag in response to occurrence of at least one multi-bit error (Signaling on the Uncorrectable Error indication in response to identifying an uncorrectable error: Gregor, col.5:15-18).
Regarding Claim 18, Gregor discloses the integrated circuit of claim 16, wherein
the MBIST controller is configured to only update the first counter once for any multiple bit error corresponding to the same access address (Updating the indicator once on encountering a multiple bit error: Gregor, col.5:17-18; An indicator necessarily cannot count past 1).
Regarding Claim 19, Gregor discloses the integrated circuit of claim 15, wherein,
after completion of a set of memory testing runs (Performing a functional operation test: Gregor, col.7:9-11),
the memory is identified as a bad part (Reporting an excess number of errors to the user: Gregor, col.7:46-49) in response to the count of uncorrectable errors in the first counter being greater than a predetermined threshold (The report being made in response to the number of errors exceeding a predetermined threshold: Gregor, col.7:37-39).
Regarding Claim 20, Konuk discloses the integrated circuit of claim 15, wherein
the memory further comprises a set of redundant columns and a set of redundant rows (Memory including one or more redundant rows and/or columns: Konuk, ¶[0024]), and
the MBIST controller (A controller: Konuk, ¶[0023]) further comprises a repair control circuit configured to:
configure the column and row repair control registers (Column and row repair control circuits: Konuk, ¶[0025]),
when the repair control register is configured for the row repair, apply the row repair during a memory testing run (Applying a row repair solution when configured for a row repair: Konuk, ¶[0028-0029]), and
when the column control register is configured for the column repair, apply the column repair during the memory testing run (Applying a column repair solution when configured for column repair: Konuk, ¶[0030]).
Response to Arguments
Applicant's arguments filed June 22, 2026 have been fully considered but they are not persuasive.
The first argument Applicant makes is that during physical (non-ECC) testing as described by Gregor, error indicators are not generated (Applicant Arguments/Remarks, page 7 ¶1). This assertion is incorrect. Gregor discloses performing a physical test between col.5:65 and col.6:37. Specifically, Gregor states, “during a physical memory test… the system 200 includes all of the same components as the system 100 and also includes inputs 105a, 105b, and 105c and outputs 106a, 106b, and 106c.” (Gregor, col.6:1-4). Gregor further states, “output 106a corresponds the Data Out, output 106b corresponds to the Correctable Error, and output 106c corresponds to the Uncorrectable Error.” (Gregor, col.6:12-16). It is clear Gregor anticipates outputting error indicators even during a physical, non-ECC, test.
Applicant acknowledges Gregor discloses counting errors, but argues the count of Gregor is a single number count of both correctable and uncorrectable errors combined (Applicant Arguments/Remarks, p. 7 ¶2). This conclusion is not supported by the text of Gregor. Gregor expressly discloses separate outputs for correctable and uncorrectable errors (Gregor, col.6:12-16). Further references to counting are ambiguous (See, for instance, “The MBIST logic… may include the accumulator 180 to count the occurrences of the Correctable Error and Uncorrectable Error indications.” Gregor, col.7:33-35). This phrasing could be read as counting each of the different type of error together, as suggested by applicant, or as two separate counts. If counting together, it would be unnecessary to provide separate indicators for the different types of errors. In either case, reading this phrase as indicating separate counts is a reasonable interpretation, and must be read under the ‘broadest reasonable interpretation’ standard.
Applicant next takes issue with the manner in which the prior office action mapped the error counter (Applicant Arguments/Remarks, p.8 ¶1). For clarity, these arguments are broken apart here:
“Gregor teaches an ‘indicator’ which is updated for an uncorrectable error… [which] is a flag… and not a counter.” This is an unnecessarily restrictive interpretation of a counter and not supported by broadest reasonable interpretation. However, in the interest of clarity, this reference has been updated to the separate counter clearly identified in Gregor, col.7:32-35.
“The first counter with respect to claim 1 was taught by a different section of Gregor, and not the indicator cited with respect to Claims 6 and 7.” This inconsistency is resolved with the additional citation.
“None of the descriptions in Gregor specifically refer to counting multiple bit errors in response to a same access address (as in claim 6) or configured to only update the first counter once for a same access address for any multiple bit error corresponding to the same access address (as in claim 7).” Gregor expressly defines an Uncorrectable Error as a multiple bit error (Gregor, col.5:12-18), expressly identifies an Uncorrectable Error indicator (Gregor, col.6:15-16), and it remains true that an indicator necessarily cannot count past one.
Applicant makes similar arguments in regards to Claim 15 and they may be addressed by similar responses.
Further, Applicant argues prior art Konuk fails to disclose iteratively running the memory test itself (Applicant Arguments/Remarks, p.10 ¶1). In fact, applicant goes so far as to state, “However, this ‘iteratively running the error check’ is not referring to iteratively performing memory testing runs, as claimed, but instead, to the recursive analysis performed on a defect matrix to locate a repair solution.” This argument fails for two reasons. First, Claim 15 does claim ‘iteratively performing memory testing runs.” Claim 15 only describes running first and second testing runs and being configured to perform repairs following each of the two runs. Second, Konuk expressly teaches running subsequent memory tests following the identification of a solution determined from the defect matrix (See, for instance, ¶¶[0045] &[0046]) and taking further corrective action if further defects are found.
Applicant's response is considered to be a bona fide attempt at a response and is being accepted as a complete response.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 10,706,950 B1 to Patrick Gallagher, et al.: Teaching a MBIST circuit configured to count uncorrectable errors through an iterative testing process.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CHRISTOPHER LANE REECE/Examiner, Art Unit 2824
/DOUGLAS KING/Primary Examiner, Art Unit 2824
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