DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 7-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (US 2021/0217763 A1).
With respect to claim 1, Lee discloses, in Figs.1-7, a memory device comprising: a core peripheral circuit structure (C2) including an internal power supply voltage line (GWL) and a first bonding metal pad (PAD2) connected to the internal power supply voltage line (GWL) (see Par.[0043] wherein the logic circuit 120 may include a row decoder 121, a page buffer circuit 122, and a peripheral circuit 123. In addition, the logic circuit 120 may include a transfer circuit 127 (i.e., the first transfer circuit); the transfer circuit 127 may be included in the circuit chip C2; see Par.[0051]-[0053] wherein the global decoder 126 may be coupled to the transfer circuit 127 through a plurality of global row lines (GWL); the global decoder 126 may transmit an operation voltage received from the peripheral circuit 123 to the transfer circuit 127 through the plurality of global row lines (GWL); the transfer circuit 127 may transmit a high voltage received from the plurality of global row lines (GWL) to the plurality of row lines (RL) in response to the row line selection signal (BLKWL)); and a cell array structure (C1) disposed on the core peripheral circuit structure (C2) and including an external power supply voltage line (RL2-RL4) for conducting an external power supply voltage applied from outside of the memory device and a second bonding metal pad (PAD1) in contact with the first bonding metal pad (PAD2), wherein the cell array structure (C1) includes a memory cell array (110_1, 110_2) and a power gating switch (TR7-9, TR13-15) connected between the external power supply voltage line (RL2-RL4) and the first bonding metal pad (PAD1), wherein the power gating switch (TR7-9, TR13-15) is located in a region (1 plane) of the cell array structure (C1) different from the memory cell array (110_1, 110_2), and the power gating switch (TR7-9, TR13-15) is configured to selectively provide the external power supply voltage to the internal power supply voltage line (RL1-RL4) (see Par.[0024]-[0031], [0044] wherein the transfer circuit 127 may include a plurality of pass transistors configured to provide a high voltage received from a global row line (to be described later) to a memory cell array 110 of the memory chip C1; see Par.[0071]-[0073] wherein second transfer circuit 115_1 may include a plurality of pass transistors TR7˜TR9 configured to provide a high voltage received from global row lines (GWL) to the memory cell array 110_1 in response to row line selection signal (BLKWL); the pass transistors TR7˜TR9 may electrically couple a plurality of global row lines (GWL) to a plurality of row lines (RL) in response to row line selection signal (BLKWL); first transfer circuit 127_1 may include a plurality of pass transistors TR10˜TR12 configured to provide a high voltage received from global row lines (GWL) to the memory cell array 110_1 in response to row line selection signal (BLKWL); the pass transistors TR10˜TR12 may electrically couple the plurality of global row lines (GWL) to a second set of row lines (RL2) in response to row line selection signal (BLKWL)).
With respect to claim 2, Lee discloses, in Figs.1-7, the memory device, wherein the power gating switch includes a plurality of switching transistors electrically connected between the external power supply voltage line and the internal power supply voltage line (see Fig.7).
With respect to claim 3, Lee discloses, in Figs.1-7, the memory device, wherein the plurality of switching transistors are connected in parallel between the external power supply voltage line and the internal power supply voltage line (see Fig.7, Par.[0063] wherein the memory chip C1 may include memory cell arrays 110_1 and 110_2, a block decoder 125_1, and second transfer circuits 115_1 and 115_2 arranged in the first direction (FD) on a first substrate (not shown); the memory chip C1 may include a first surface S11 and a parallel or substantially parallel second surface S12 in the first direction (FD)).
With respect to claim 7, Lee discloses, in Figs.1-7, a memory device comprising: a core peripheral circuit structure (C2) including an internal ground voltage line (GWL) and a first bonding metal pad (PAD2) connected to the internal ground voltage line (see Par.[0043] wherein the logic circuit 120 may include a row decoder 121, a page buffer circuit 122, and a peripheral circuit 123. In addition, the logic circuit 120 may include a transfer circuit 127 (i.e., the first transfer circuit); the transfer circuit 127 may be included in the circuit chip C2; see Par.[0051]-[0053] wherein the global decoder 126 may be coupled to the transfer circuit 127 through a plurality of global row lines (GWL); the global decoder 126 may transmit an operation voltage received from the peripheral circuit 123 to the transfer circuit 127 through the plurality of global row lines (GWL); the transfer circuit 127 may transmit a high voltage received from the plurality of global row lines (GWL) to the plurality of row lines (RL) in response to the row line selection signal (BLKWL)); and a cell array structure (C1) disposed on the core peripheral circuit structure (C2) and including an external ground voltage line (RL) for conducting an external ground voltage applied from outside of the memory device (110) and a second bonding metal pad (PAD1) in contact with the first bonding metal pad (PAD2), wherein the cell array structure includes a memory cell array and a power gating switch connected between the external ground voltage line and the first bonding metal pad, wherein the power gating switch is located in a region of the cell array structure different from the memory cell array, and the power gating switch is configured to selectively provide the external ground voltage to the internal ground voltage line (see Par.[0024]-[0031], [0044] wherein the transfer circuit 127 may include a plurality of pass transistors configured to provide a high voltage received from a global row line (to be described later) to a memory cell array 110 of the memory chip C1; see Par.[0071]-[0073] wherein second transfer circuit 115_1 may include a plurality of pass transistors TR7˜TR9 configured to provide a high voltage received from global row lines (GWL) to the memory cell array 110_1 in response to row line selection signal (BLKWL); the pass transistors TR7˜TR9 may electrically couple a plurality of global row lines (GWL) to a plurality of row lines (RL) in response to row line selection signal (BLKWL); first transfer circuit 127_1 may include a plurality of pass transistors TR10˜TR12 configured to provide a high voltage received from global row lines (GWL) to the memory cell array 110_1 in response to row line selection signal (BLKWL); the pass transistors TR10˜TR12 may electrically couple the plurality of global row lines (GWL) to a second set of row lines (RL2) in response to row line selection signal (BLKWL)).
With respect to claim 8, Lee discloses, in Figs.1-7, the memory device, wherein the power gating switch includes a plurality of switching transistors electrically connected between the external ground voltage line and the internal ground voltage line (see Fig.7).
With respect to claim 9, Lee discloses, in Figs.1-7, the memory device, wherein the plurality of switching transistors are connected in parallel between the external ground voltage line and the internal ground voltage line (see Fig.7, Par.[0063] wherein the memory chip C1 may include memory cell arrays 110_1 and 110_2, a block decoder 125_1, and second transfer circuits 115_1 and 115_2 arranged in the first direction (FD) on a first substrate (not shown); the memory chip C1 may include a first surface S11 and a parallel or substantially parallel second surface S12 in the first direction (FD)).
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Murakami (US 2023/0083442 A1).
With respect to claim 1, Murakami discloses, in Figs.1-26, a memory device comprising: a core peripheral circuit structure (C.sub.P) including an internal power supply voltage line (V.sub.cc) and a first bonding metal pad (P.sub.12) connected to the internal power supply voltage line (V.sub.cc) (see Par.[0047]-[0051] wherein the peripheral circuit PC includes a voltage generation circuit VG, a row decoder RD, a sense amplifier module SAM, and a sequencer SQC; the voltage generation circuit VG includes, for example, a step-down circuit and a step-up circuit; each of the step-down circuit and the step-up circuits is connected to power-source voltage supply lines; a power-source voltage V.sub.cc and a ground voltage V.sub.ss are supplied to the power-source voltage supply lines; see Par.[0060]-[0067] wherein the memory die MD includes a chip C.sub.M including a memory cell array MCA and a chip C.sub.P including peripheral circuits); and a cell array structure (C.sub.M) disposed on the core peripheral circuit structure (C.sub.P) and including an external power supply voltage line (V.sub.CCQ) for conducting an external power supply voltage applied from outside of the memory device (C.sub.M) and a second bonding metal pad (P.sub.11) in contact with the first bonding metal pad (P.sub.12), wherein the cell array structure (C.sub.M) includes a memory cell array and a power gating switch/(memory transistor) connected between the external power supply voltage line (V.sub.CCQ) and the first bonding metal pad (P.sub.12), wherein the power gating switch is located in a region of the cell array structure different from the memory cell array, and the power gating switch is configured to selectively provide the external power supply voltage to the internal power supply voltage line (see Par.[0057]-[0058] wherein the plurality of input circuits, the plurality of output circuits, the shift register, and the buffer circuit are connected to terminals to which the power-source voltage V.sub.CCQ and the ground voltage V.sub.ss are supplied, respectively; see Par.[0065] wherein the chip C.sub.M includes four memory cell array regions R.sub.MCA arranged in the X direction and the Y direction. The memory cell array region R.sub.MCA includes a memory hole region R.sub.MH in which the memory transistor is provided, and a hookup region R.sub.HU provided on one side (for example, positive side in the X direction in FIG. 7) and the other side (for example, negative side in the X direction in FIG. 7) of the memory hole region R.sub.MH in the X direction; further, a plurality of input/output circuit regions R.sub.IO provided corresponding to the plurality of bonding pad electrodes P.sub.x (FIGS. 2, 3, and 5) are provided in a portion of the peripheral region R).
With respect to claim 2, Murakami discloses, in Figs.1-26, the memory device, wherein the power gating switch includes a plurality of switching transistors electrically connected between the external power supply voltage line and the internal power supply voltage line (see Par.[0065] wherein the chip C.sub.M includes four memory cell array regions R.sub.MCA arranged in the X direction and the Y direction. The memory cell array region R.sub.MCA includes a memory hole region R.sub.MH in which the memory transistor is provided, and a hookup region R.sub.HU provided on one side (for example, positive side in the X direction in FIG. 7) and the other side (for example, negative side in the X direction in FIG. 7) of the memory hole region R.sub.MH in the X direction; further, a plurality of input/output circuit regions R.sub.IO provided corresponding to the plurality of bonding pad electrodes P.sub.x (FIGS. 2, 3, and 5) are provided in a portion of the peripheral region R).
With respect to claim 3, Murakami discloses, in Figs.1-26, the memory device, wherein the plurality of switching transistors are connected in parallel between the external power supply voltage line and the internal power supply voltage line (see Fig.9).
With respect to claim 4, Murakami discloses, in Figs.1-26, the memory device, further comprising a plurality of vertical channel transistors, each of the vertical channel transistors comprising: a portion of an upper substrate (220) (see Par.[0100] wherein the chip C.sub.P includes a semiconductor substrate 200 and a transistor layer L.sub.TR provided above the semiconductor substrate 200, and a plurality of wiring layers 220, 230, 240, 250 provided above the transistor layer L.sub.TR); a bit line (BL) disposed on the upper substrate (220) and extending in a second direction/(y-direction) intersecting with a first direction/(x-direction); a pair of active patterns (120) disposed on the bit line (see Par.[0078] wherein the semiconductor layer 120 functions as, for example, channel regions of a plurality of memory transistors; see Par.[0088] wherein the wiring layer 140 includes a plurality of wirings 141; some of the plurality of wirings 141 function as the bit lines BL); a back gate electrode (121-122) located between the pair of active patterns (120) and extending in the first direction/(x-direction); and a pair of word lines (110) disposed outside the pair of active patterns (120) and extending in the first direction/(x-direction) (see Par.[0077] wherein the plurality of conductive layers 110 function as, for example, word lines and gate electrodes of a plurality of memory transistors connected to the word lines; see Par.[0079] wherein an impurity region (not illustrated) containing N-type impurities such as phosphorus (P) is provided at a lower end portion of the semiconductor layer 120; the impurity region is connected to the bit line BL via a contact 121 and a contact 122).
With respect to claim 5, Murakami discloses, in Figs.1-26, the memory device, wherein the power gating switch includes a plurality of switching transistors electrically connected between the external power supply voltage line and the internal power supply voltage line, and each switching transistor of the plurality of switching transistors has a same structure as the plurality of vertical channel transistors, and the pair of active patterns of the plurality of switching transistors and the pair of active patterns of the plurality of vertical channel transistors have opposite conductivity types (see Par.[0079]-[0080] wherein an impurity region containing N-type impurities such as phosphorus (P) or P-type impurities such as boron (B) is provided in the upper end portion of the semiconductor layer 120).
With respect to claim 6, Murakami discloses, in Figs.1-26, the memory device, wherein the memory cell array includes a shielding bit line (150, 160) located between a plurality of bit lines (BL), including the bit line, and below the plurality of bit lines (see Par.[0087] wherein The plurality of wirings in the wiring layers 140, 150, and 160 are electrically connected to at least one of the components in the memory cell array layer L.sub.MCA and the components in the chip C.sub.P, for example).
With respect to claim 7, Murakami discloses, in Figs.1-26, a memory device comprising: a core peripheral circuit structure (C.sub.P) including an internal ground voltage line (V.sub.ss) and a first bonding metal pad (P.sub.12) connected to the internal ground voltage line (V.sub.ss) (see Par.[0047]-[0051] wherein the peripheral circuit PC includes a voltage generation circuit VG, a row decoder RD, a sense amplifier module SAM, and a sequencer SQC; the voltage generation circuit VG includes, for example, a step-down circuit and a step-up circuit; each of the step-down circuit and the step-up circuits is connected to power-source voltage supply lines; a power-source voltage V.sub.cc and a ground voltage V.sub.ss are supplied to the power-source voltage supply lines; see Par.[0060]-[0067] wherein the memory die MD includes a chip C.sub.M including a memory cell array MCA and a chip C.sub.P including peripheral circuits); and a cell array structure (C.sub.M) disposed on the core peripheral circuit structure (C.sub.P) and including an external ground voltage line (V.sub.ss) for conducting an external ground voltage applied from outside of the memory device and a second bonding metal pad (P.sub.11) in contact with the first bonding metal pad (p.sub.12), wherein the cell array structure includes a memory cell array and a power gating switch connected between the external ground voltage line (V.sub.ss line) and the first bonding metal pad (P.sub.11), wherein the power gating switch is located in a region of the cell array structure different from the memory cell array, and the power gating switch is configured to selectively provide the external ground voltage to the internal ground voltage line (see Par.[0057]-[0058] wherein the plurality of input circuits, the plurality of output circuits, the shift register, and the buffer circuit are connected to terminals to which the power-source voltage V.sub.CCQ and the ground voltage V.sub.ss are supplied, respectively; see Par.[0065] wherein the chip C.sub.M includes four memory cell array regions R.sub.MCA arranged in the X direction and the Y direction. The memory cell array region R.sub.MCA includes a memory hole region R.sub.MH in which the memory transistor is provided, and a hookup region R.sub.HU provided on one side (for example, positive side in the X direction in FIG. 7) and the other side (for example, negative side in the X direction in FIG. 7) of the memory hole region R.sub.MH in the X direction; further, a plurality of input/output circuit regions R.sub.IO provided corresponding to the plurality of bonding pad electrodes P.sub.x (FIGS. 2, 3, and 5) are provided in a portion of the peripheral region R).
With respect to claim 8, Murakami discloses, in Figs.1-26, the memory device, wherein the power gating switch includes a plurality of switching transistors electrically connected between the external ground voltage line and the internal ground voltage line (see Par.[0057]-[0058] wherein the plurality of input circuits, the plurality of output circuits, the shift register, and the buffer circuit are connected to terminals to which the power-source voltage V.sub.CCQ and the ground voltage V.sub.ss are supplied, respectively; see Par.[0065] wherein the chip C.sub.M includes four memory cell array regions R.sub.MCA arranged in the X direction and the Y direction. The memory cell array region R.sub.MCA includes a memory hole region R.sub.MH in which the memory transistor is provided, and a hookup region R.sub.HU provided on one side (for example, positive side in the X direction in FIG. 7) and the other side (for example, negative side in the X direction in FIG. 7) of the memory hole region R.sub.MH in the X direction; further, a plurality of input/output circuit regions R.sub.IO provided corresponding to the plurality of bonding pad electrodes P.sub.x (FIGS. 2, 3, and 5) are provided in a portion of the peripheral region R).
With respect to claim 9, Murakami discloses, in Figs.1-26, the memory device, wherein the plurality of switching transistors are connected in parallel between the external power supply voltage line and the internal power supply voltage line (see Fig.9).
With respect to claim 10, Murakami discloses, in Figs.1-26, the memory device, further comprising a plurality of vertical channel transistors, each of the vertical channel transistors comprising: a portion of an upper substrate (220) (see Par.[0100] wherein the chip C.sub.P includes a semiconductor substrate 200 and a transistor layer L.sub.TR provided above the semiconductor substrate 200, and a plurality of wiring layers 220, 230, 240, 250 provided above the transistor layer L.sub.TR); a bit line (BL) disposed on the upper substrate (220) and extending in a second direction/(y-direction) intersecting with a first direction/(x-direction); a pair of active patterns (120) disposed on the bit line (see Par.[0078] wherein the semiconductor layer 120 functions as, for example, channel regions of a plurality of memory transistors; see Par.[0088] wherein the wiring layer 140 includes a plurality of wirings 141; some of the plurality of wirings 141 function as the bit lines BL); a back gate electrode (121-122) located between the pair of active patterns (120) and extending in the first direction/(x-direction); and a pair of word lines (110) disposed outside the pair of active patterns (120) and extending in the first direction/(x-direction) (see Par.[0077] wherein the plurality of conductive layers 110 function as, for example, word lines and gate electrodes of a plurality of memory transistors connected to the word lines; see Par.[0079] wherein an impurity region (not illustrated) containing N-type impurities such as phosphorus (P) is provided at a lower end portion of the semiconductor layer 120; the impurity region is connected to the bit line BL via a contact 121 and a contact 122).
With respect to claim 11, Murakami discloses, in Figs.1-26, the memory device, wherein the power gating switch includes a plurality of switching transistors electrically connected between the external power supply voltage line and the internal power supply voltage line, and each switching transistor of the plurality of switching transistors has a same structure as the plurality of vertical channel transistors, and the pair of active patterns of the plurality of switching transistors and the pair of active patterns of the plurality of vertical channel transistors have same conductivity types (see Par.[0079]-[0080] wherein an impurity region containing N-type impurities such as phosphorus (P) or P-type impurities such as boron (B) is provided in the upper end portion of the semiconductor layer 120).
With respect to claim 12, Murakami discloses, in Figs.1-26, the memory device, wherein the memory cell array includes a shielding bit line (150, 160) located between a plurality of bit lines (BL), including the bit line, and below the plurality of bit lines (see Par.[0087] wherein The plurality of wirings in the wiring layers 140, 150, and 160 are electrically connected to at least one of the components in the memory cell array layer L.sub.MCA and the components in the chip C.sub.P, for example).
With respect to claim 13, Murakami discloses, in Figs.1-26, a memory device comprising: a core peripheral circuit structure (C.sub.P) including an internal power supply voltage line (V.sub.cc), an internal ground voltage line (V.sub.ss), a first bonding metal pad (P.sub.12) connected to the internal power supply voltage line (V.sub.cc), and a second bonding metal pad (P.sub.11) connected to the internal ground voltage line (V.sub.cc) (see Par.[0047]-[0051] wherein the peripheral circuit PC includes a voltage generation circuit VG, a row decoder RD, a sense amplifier module SAM, and a sequencer SQC; the voltage generation circuit VG includes, for example, a step-down circuit and a step-up circuit; each of the step-down circuit and the step-up circuits is connected to power-source voltage supply lines; a power-source voltage V.sub.cc and a ground voltage V.sub.ss are supplied to the power-source voltage supply lines; see Par.[0060]-[0067] wherein the memory die MD includes a chip C.sub.M including a memory cell array MCA and a chip C.sub.P including peripheral circuits); and a cell array structure (C.sub.M) overlapping the core peripheral circuit structure (C.sub.P) in a vertical direction and including an external power supply voltage line (V.sub.CCQ) for conducting an external power supply voltage applied from outside of the memory device, an external ground voltage line (V.sub.ss) for conducting an external ground voltage applied from the outside of the memory device, a third bonding metal pad (240-241) in contact with the first bonding metal pad (P.sub.12), and a fourth bonding metal pad (150) in contact with the second bonding metal pad (P.sub.11), wherein the cell array structure includes a memory cell array including a plurality of memory cells and a power gating switch/(memory transistor) located in a region of the cell array structure different from the memory cell array, the power gating switch includes a first power gating circuit connected between the external power supply voltage line and the third bonding metal pad and a second power gating circuit connected between the external ground voltage line and the fourth bonding metal pad, and the first power gating circuit is configured to selectively provide the external power supply voltage to the internal power supply voltage line, and the second power gating circuit is configured to selectively provide the external ground voltage to the internal ground voltage line (see Par.[0057]-[0058] wherein the plurality of input circuits, the plurality of output circuits, the shift register, and the buffer circuit are connected to terminals to which the power-source voltage V.sub.CCQ and the ground voltage V.sub.ss are supplied, respectively; see Par.[0065] wherein the chip C.sub.M includes four memory cell array regions R.sub.MCA arranged in the X direction and the Y direction. The memory cell array region R.sub.MCA includes a memory hole region R.sub.MH in which the memory transistor is provided, and a hookup region R.sub.HU provided on one side (for example, positive side in the X direction in FIG. 7) and the other side (for example, negative side in the X direction in FIG. 7) of the memory hole region R.sub.MH in the X direction; further, a plurality of input/output circuit regions R.sub.IO provided corresponding to the plurality of bonding pad electrodes P.sub.x (FIGS. 2, 3, and 5) are provided in a portion of the peripheral region R; see Par.[0110], [0119], [0122] wherein the wiring layer 240 includes a plurality of wirings 241; the plurality of wirings 241 may include, for example, a stacked film of a barrier conductive film made of titanium nitride (TiN) or the like and a metal film made of copper (Cu) or the like; among the plurality of wirings 241, the wirings that are electrically connected to the bonding pad electrode P.sub.x (V.sub.ss) may be arranged more densely than other regions in the region near the high-speed I/F circuit; similarly, among the plurality of wirings 241, the wirings that are electrically connected to the bonding pad electrode P.sub.x (V.sub.CCQ) may be arranged more densely than other regions in the region near the high-speed I/F circuit; see Par.[0136] wherein it is possible to suitably operate the input/output control circuit I/O while enhancing the degree of freedom in design in the wiring layers 140, 150, 220, 230, and 240).
With respect to claim 14, Murakami discloses, in Figs.1-26, the memory device, wherein the first power gating circuit includes a plurality of first switching transistors electrically connected between the external power supply voltage line and the internal power supply voltage line, and the second power gating circuit includes a plurality of second switching transistors electrically connected between the external ground voltage line and the internal ground voltage line (see Par.[0057]-[0058] wherein the plurality of input circuits, the plurality of output circuits, the shift register, and the buffer circuit are connected to terminals to which the power-source voltage V.sub.CCQ and the ground voltage V.sub.ss are supplied, respectively; see Par.[0065] wherein the chip C.sub.M includes four memory cell array regions R.sub.MCA arranged in the X direction and the Y direction. The memory cell array region R.sub.MCA includes a memory hole region R.sub.MH in which the memory transistor is provided, and a hookup region R.sub.HU provided on one side (for example, positive side in the X direction in FIG. 7) and the other side (for example, negative side in the X direction in FIG. 7) of the memory hole region R.sub.MH in the X direction; further, a plurality of input/output circuit regions R.sub.IO provided corresponding to the plurality of bonding pad electrodes P.sub.x (FIGS. 2, 3, and 5) are provided in a portion of the peripheral region R; see Par.[0110], [0119], [0122] wherein the wiring layer 240 includes a plurality of wirings 241; the plurality of wirings 241 may include, for example, a stacked film of a barrier conductive film made of titanium nitride (TiN) or the like and a metal film made of copper (Cu) or the like; among the plurality of wirings 241, the wirings that are electrically connected to the bonding pad electrode P.sub.x (V.sub.ss) may be arranged more densely than other regions in the region near the high-speed I/F circuit; similarly, among the plurality of wirings 241, the wirings that are electrically connected to the bonding pad electrode P.sub.x (V.sub.CCQ) may be arranged more densely than other regions in the region near the high-speed I/F circuit; see Par.[0136] wherein it is possible to suitably operate the input/output control circuit I/O while enhancing the degree of freedom in design in the wiring layers 140, 150, 220, 230, and 240).
With respect to claim 15, Murakami discloses, in Figs.1-26, the memory device, wherein the first switching transistors include PMOS transistors (see Par.[0078]-[0080] wherein the semiconductor layer 120 functions as, for example, channel regions of a plurality of memory transistors; the semiconductor layer 120 is a semiconductor layer made of polycrystalline silicon (Si), for example an impurity region containing N-type impurities such as phosphorus (P) or P-type impurities such as boron (B) is provided in the upper end portion of the semiconductor layer 120).
With respect to claim 16, Murakami discloses, in Figs.1-26, the memory device, wherein the second switching transistors include NMOS transistors (see Par.[0078]-[0080] wherein the semiconductor layer 120 functions as, for example, channel regions of a plurality of memory transistors; the semiconductor layer 120 is a semiconductor layer made of polycrystalline silicon (Si), for example an impurity region containing N-type impurities such as phosphorus (P) or P-type impurities such as boron (B) is provided in the upper end portion of the semiconductor layer 120).
With respect to claim 17, Murakami discloses, in Figs.1-26, the memory device, wherein the plurality of first switching transistors are connected in parallel between the external power supply voltage line and the internal power supply voltage line and the plurality of second switching transistors are arranged connected in parallel between the external ground voltage line and the internal ground voltage line (see Fig.9).
With respect to claim 18, Murakami discloses, in Figs.1-26, the memory device, further comprising a plurality of vertical channel transistors, each of the vertical channel transistors comprising: a portion of an upper substrate (220) (see Par.[0100] wherein the chip C.sub.P includes a semiconductor substrate 200 and a transistor layer L.sub.TR provided above the semiconductor substrate 200, and a plurality of wiring layers 220, 230, 240, 250 provided above the transistor layer L.sub.TR); a bit line (BL) disposed on the upper substrate (220) and extending in a second direction/(y-direction) intersecting with a first direction/(x-direction); a pair of active patterns (120) disposed on the bit line (see Par.[0078] wherein the semiconductor layer 120 functions as, for example, channel regions of a plurality of memory transistors; see Par.[0088] wherein the wiring layer 140 includes a plurality of wirings 141; some of the plurality of wirings 141 function as the bit lines BL); a back gate electrode (121-122) located between the pair of active patterns (120) and extending in the first direction/(x-direction); and a pair of word lines (110) disposed outside the pair of active patterns (120) and extending in the first direction/(x-direction) (see Par.[0077] wherein the plurality of conductive layers 110 function as, for example, word lines and gate electrodes of a plurality of memory transistors connected to the word lines; see Par.[0079] wherein an impurity region (not illustrated) containing N-type impurities such as phosphorus (P) is provided at a lower end portion of the semiconductor layer 120; the impurity region is connected to the bit line BL via a contact 121 and a contact 122).
With respect to claim 19, Murakami discloses, in Figs.1-26, the memory device, wherein the memory cell array includes a shielding bit line located between a plurality of bit lines, including the bit line, and below the plurality of bit lines (see Par.[0087] wherein The plurality of wirings in the wiring layers 140, 150, and 160 are electrically connected to at least one of the components in the memory cell array layer L.sub.MCA and the components in the chip C.sub.P, for example).
With respect to claim 20, Murakami discloses, in Figs.1-26, the memory device, wherein the core peripheral circuit structure includes core peripheral circuits different than the memory cell array, and the core peripheral circuits are connected to the internal power supply voltage line and the internal ground voltage line (see Par.[0047]-[0051] wherein the peripheral circuit PC includes a voltage generation circuit VG, a row decoder RD, a sense amplifier module SAM, and a sequencer SQC; the voltage generation circuit VG includes, for example, a step-down circuit and a step-up circuit; each of the step-down circuit and the step-up circuits is connected to power-source voltage supply lines; a power-source voltage V.sub.cc and a ground voltage V.sub.ss are supplied to the power-source voltage supply lines; see Par.[0060]-[0067] wherein the memory die MD includes a chip C.sub.M including a memory cell array MCA and a chip C.sub.P including peripheral circuits).
Citation of Pertinent Prior Art
The prior art made of record (e.g.; see PTO-892) and not relied upon is considered pertinent to applicant's disclosure.
Examiner’s Telephone/Fax Contacts
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOULOUCOULAYE INOUSSA whose telephone number is (571)272-0596. The examiner can normally be reached Monday-Friday (10-18).
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/Mouloucoulaye Inoussa/ Primary Examiner, Art Unit 2818
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