DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/22/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 7 is objected to because of the following informalities:
Claim 7 recites the limitation “wherein each of the plurality of semiconductor packages is: a lower surface of an edge portion of the molding layer and a lower surface of the redistribution layer are exposed”, in lines 1-4 of the claim, which appears to be grammatically incorrect, and thus the Examiner suggests amending the limitation to “wherein for each of the plurality of semiconductor packages: [[is:]] a lower surface of an edge portion of the molding layer and a lower surface of the redistribution layer are exposed”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “the distance” in line 11 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 8 recites the limitation “the surface roughness” in line 1 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 20 recites the limitation “the distance” in line 2 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Note the dependent claims 2-8 necessarily inherit the indefiniteness of the claims on which they depend.
Allowable Subject Matter
Claims 9-19 are allowed.
Regarding independent claim 9, Huang et al. (US 2019/0164783 A1, hereinafter “Huang”) discloses a method of fabricating a semiconductor package, the method comprising:
forming an adhesive layer (i.e., “adhesive layer”- ¶0014) on a carrier substrate 101 (“carrier”- ¶0012) (see Fig. 1);
forming a redistribution layer 140’ (“redistribution structure”- ¶0034) on the adhesive layer (see Fig. 6);
removing at least a portion of the redistribution layer 140’ to form a through portion 311/313 (“openings”- ¶0038) with a grid pattern on a plane (¶0038) (see Figs. 7A-7B);
mounting semiconductor chips 162 (“semiconductor dies”- ¶0047) on the redistribution layer 140’ (see Fig. 9); and
forming a molding layer 165 (“molding material”- ¶0047) covering the redistribution layer 140’, and the semiconductor chips 162 (see Fig. 9);
separating the adhesive layer and the carrier substrate 101 from the redistribution layer 140’ (¶0043) (see Fig. 8); and
cutting between the semiconductor chips 162 along a scribe lane overlapping the through portion 311/313 and separating it into a plurality of semiconductor packages 500 (“packages”- ¶0050) (¶¶0050-0051) (see Fig. 10-11).
Huang does not expressly disclose forming the molding layer covering the carrier substrate, cutting the molding layer between the semiconductor chips along a scribe lane overlapping the through portion and separating it into a plurality of semiconductor packages, and wherein an angle between a side surface of the redistribution layer and a lower surface of the redistribution layer of each of the semiconductor packages is an acute angle.
Thus, regarding independent claim 9, the claim is allowed, because the prior art of record including Haung, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “forming a molding layer covering the carrier substrate”, “cutting the molding layer between the semiconductor chips along a scribe lane overlapping the through portion and separating it into a plurality of semiconductor packages” and “wherein an angle between a side surface of the redistribution layer and a lower surface of the redistribution layer of each of the semiconductor packages is an acute angle”.
Claims 10-16 are allowed as being dependent on allowed claim 9.
Regarding independent claim 17, Huang discloses a method of fabricating a semiconductor package, the method comprising:
forming an adhesive layer (i.e., “adhesive layer”- ¶0014) on a carrier substrate 101 (“carrier”- ¶0012) (see Fig. 1);
forming a temporary insulating layer 110 (“dielectric layer”- ¶0013) on the adhesive layer (¶0014) (see Fig. 1);
forming an etch stop layer on the temporary insulating layer;
forming a redistribution layer 140’ (“redistribution structure”- ¶0034) (see Fig. 6);
removing at least a portion of the redistribution layer 140’ to form a through portion 311/313 (“openings”- ¶0038) with a grid pattern on a plane (¶0038), using an ultraviolet laser (¶0040) (see Figs. 7A-7B),
mounting semiconductor chips 162 (“semiconductor dies”- ¶0047) on the redistribution layer 140’ (see Fig. 9); and
forming a molding layer 165 (“molding material”- ¶0047) covering the redistribution layer 140’, and the semiconductor chips 162 (see Fig. 9).
Huang does not expressly disclose forming an etch stop layer on the temporary insulating layer, forming the redistribution layer on the etch stop layer, wherein the through portion exposes the above etch stop layer, forming the molding layer covering the etch stop layer and wherein a wavelength of the ultraviolet laser is 150 nm or more and 400 nm or less.
Thus, regarding independent claim 17, the claim is allowed, because the prior art of record including Haung, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “forming an etch stop layer on the temporary insulating layer”, “forming a redistribution layer on the etch stop layer”, “wherein the through portion exposes the above etch stop layer”, “forming a molding layer covering the etch stop layer” and “wherein a wavelength of the ultraviolet laser is 150 nm or more and 400 nm or less”.
Claims 18-19 are allowed as being dependent on allowed claim 17.
Claims 1-8 would be allowable if rewritten or amended to overcome the objected subject matter and/or the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Regarding independent claim 1, Huang discloses a method of fabricating a semiconductor package, the method comprising:
forming a redistribution layer 140’ (“redistribution structure”- ¶0034) on a carrier substrate 101 (“carrier”- ¶0012) (see Fig. 6);
removing at least a portion of the redistribution layer 140’ to form a through portion 311/313 (“openings”- ¶0038) with a grid pattern on a plane (¶0038) (see Figs. 7A-7B);
mounting semiconductor chips 162 (“semiconductor dies”- ¶0047) on the redistribution layer 140’ (see Fig. 9); and
forming a molding layer 165 (“molding material”- ¶0047) covering the redistribution layer 140’, and the semiconductor chips 162 (see Fig. 9),
wherein the molding layer 165 covers a bottom surface of the through portion 311/313 (see Fig. 9).
Huang does not expressly disclose forming the molding layer covering the carrier substrate, wherein the bottom surface of the through portion and a bottom surface of the redistribution layer are coplanar with each other, and wherein a width of the through portion is wider as the distance from the carrier substrate increases.
Thus, regarding independent claim 1 (which claims 2-8 depend from), the prior art of record including Huang, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “forming a molding layer covering the carrier substrate”, “the bottom surface of the through portion and a bottom surface of the redistribution layer are coplanar with each other” and “wherein a width of the through portion is wider as the distance from the carrier substrate increases”.
Claim 20 (which depends from allowed claim 17) would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Shih et al. (US 9,570,369 B1), which discloses a method of fabricating a semiconductor package comprising removing a portion of a redistribution layer to form a through portion.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C CHANG whose telephone number is (571)272-6132. The examiner can normally be reached Mon- Fri 12pm-10pm.
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/JAY C CHANG/ Primary Examiner, Art Unit 2817
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