DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Response to Amendment
Applicant’s response filed on 06/24/2026 in which claim 18 is amended, claims 1-17 are canceled, and claims 34-37 are added has been entered of record.
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Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(e) the invention was described in (1) an application for patent, published under section 122(b), by another filed in the United States before the invention by the applicant for patent or (2) a patent granted on an application for patent by another filed in the United States before the invention by the applicant for patent, except that an international application filed under the treaty defined in section 351(a) shall have the effects for purposes of this subsection of an application filed in the United States only if the international application designated the United States and was published under Article 21(2) of such treaty in the English language.
Claims 18-37 are rejected under pre-AIA 35 U.S.C. 102(e) as being anticipated by Suh (US Pub. 2011/0079923).
Regarding claim 18, Fig. 1 of Suh discloses a system comprising:
a processor [710, Fig. 7, or 204 or 214 in Fig. 2]; and
a plurality of stacked memory die [Die 1 to Die 4, Fig. 1] coupled to a plurality of channels [206, 208, 210, 212 in Fig. 2, or 306 in Fig. 3] the processor [204 or 214];
wherein each of the stacked memory die comprises:
a substrate [110];
a first face [top] having a plurality of terminals [116, 118, 120, 122];
a second face [bottom] opposite the first face having a plurality of terminals [F1 to F4] aligned with the plurality of terminals [116, 118, 120, 122] on the first face, the plurality of terminals on the second face [F1 to F4] being couples to different ones of the plurality of channels [as shows in Fig. 2, 1st to 4th TSV is connected to each channel 206, 208, 210, and 212 respectively. Therefore, F1 to F4 also connects to 206, 208, 210, and 212 via the TSV];
a plurality of TSVs [1st column TSV to 4th column TSV] aligned with and connected to the plurality of terminals on the first face [clearly shows in Fig. 1]; and
a plurality of interconnects [the wire connections in layer 112] forming a signal path between the plurality of TSVs and respective terminals among the plurality of terminals on the second face that are not aligned [as shows in Fig. 1, the signal paths connects 116 to F4, 118 to F1, 120 to F2, and 122 to F3. They are not aligned] with the plurality of terminals on the first face [116, 118, 120, and 120] connected to respective TSVs among the plurality of TSVs.
Regarding claim 19, Fig. 7 of Suh discloses a system element [710] stacked with the plurality of stacked memory die.
Regarding claim 20, Fig. 7 of Suh discloses wherein the system element includes the processor [paragraph 0042].
Regarding claim 21, Fig. 7 of Suh discloses wherein the stacked memory die are DRAM die [paragraph 0058].
Regarding claim 22, Fig. 2 of Suh discloses wherein each of the stacked memory die further comprises a plurality of drivers [circuit 202 to drive chip select signals] connected to the plurality of interconnects.
Regarding claim 23, Fig. 2 of Suh discloses wherein the plurality of drivers are data drivers [chip ID can be considered data].
Regarding claim 24, Fig. 1 of Suh discloses wherein the plurality of terminals on the first face and the plurality of terminals on the second face are data terminals [since data are transferred between each die through the terminals, they are considered data terminals].
Regarding claim 25, Fig. 1 of Suh discloses wherein the plurality of interconnects includes a wrap around interconnect to connect a last terminal [116] on the first face with a first terminal [F4] on the second face.
Regarding claim 26, Fig. 1 of Suh discloses a first terminal at a first position [122] on the first face of each stacked memory die is connected to a second terminal [F3] at a second position on the second face of each stacked memory die; a second terminal at a second position [120] on the first face of each stacked memory die is connected to a third terminal [F2] at a third position on the second face of each stacked memory die; a third terminal at a third position [118] on the first face of each stacked memory die is connected to a fourth terminal [F1] at a fourth position on the second face of each stacked memory die; and a fourth terminal [116] at a fourth position on the first face of each stacked memory die is connected to a first terminal [F4] at a first position on the second face of each stacked memory die.
Regarding claim 27, Fig. 1 of Suh discloses wherein the plurality of stacked memory die comprise four [Die 1 to Die 4] stacked memory die [paragraph 0030].
Regarding claim 28, paragraph 0030 of Suh discloses any number of die can be stacked. Therefore, it is inherent that there can be eight stacked memory dies.
Regarding claim 29, Fig. 7 of Suh discloses wherein the processor [710] include an operating platform for executing applications, device functions or both applications and device functions [paragraph 0048].
Regarding claim 30, Fig. 7 of Suh discloses wherein the processor performs operations related to input/output or power management [as shows in Fig. 7, there are input/output devices and power supply. Therefore, operations related to input/output or power management is inherent].
Regarding claim 31, Fig. 7 of Suh discloses wherein the input/output is related to audio [SPEAKER], display [DISPLAY] or both audio and display functions.
Regarding claim 32, Fig. 7 of Suh discloses wherein the processor [710] and the plurality of stacked memory die are included in a cell phone [WIRELESS INTERFACE, MICROPHONE].
Regarding claim 33, Fig. 7 of Suh discloses wherein processing operations performed by the processor include the execution of an operating platform or operating system on which applications, device functions, or both are executed [paragraph 0048].
Regarding claim 34, Fig. 1 and Fig. 2 of Suh discloses wherein the plurality of stacked memory die [Die 1 to Die 4] are configured to drive the plurality of channel via the plurality of terminals on the second face [since 1st to 4th TSV signals are inputted to processor 204, the signals are inherently driven].
Regarding claim 35, Fig. 1 of Suh discloses wherein the plurality of stacked memory die [Die 1 to Die 4] includes drivers configured to drive the plurality of channels [since signals are driven, drivers are inherent] via the plurality of terminals on the second face.
Regarding claim 36, Fig. 1 of Suh discloses wherein each of the plurality of stacked memory die [Die 1 to Die 4] includes at least one driver configured to drive one or more of the plurality of channels [since the signals are driven to the channel 206 to 212, a driver is inherent], such that each of the plurality of stacked memory die is configured to drive different ones of the plurality of channels.
Regarding claim 37, Fig. 1 of Suh discloses wherein each of the plurality of stacked memory die [Die 1 to Die 4] includes at least one driver [since signals are driven to channels 206 to 212, a driver is inherent] configured to drive one or more of the plurality of channels via the plurality of terminals on the second face [F1 to F4], such that each of the plurality of stacked memory die is configured to drive different ones of the plurality of channels.
Response to Arguments
Applicant's arguments filed 06/24/2026 have been fully considered but they are not persuasive.
Applicant argues that Suh teaches a common access channel structure 306, but does not specifically disclose “the plurality of terminals on the second face being coupled to different ones of the plurality of channels”.
Applicant is reminded that the claims are examined in light of broadest reasonable interpretation. In addition, although the claims are examined in light of specification, limitations from specification are not read into the claims. See MPEP 2111. Applicant claims a processor, but does not specify what kind of processor and its structure. Therefore, any circuit that process signal can be considered a processor. Therefore, circuit 204 or 214 in Fig. 2 can be considered a processor. As shows in Fig. 1 and Fig. 2, each terminals [F1 to F4] on the second face is connected to a TSV groups (1st TSV to 4th TSV), and each TSV is connected to a channel 206, 208, 210, and 212 respectively.
In addition, as shows in Fig. 3 of Suh, the common channel structure 306 has plurality of channels 308. As discloses in paragraphs 0023, 0028, 0031, and 0034, the Chip_ID[0:3] and Data are transferred to each memory dies via the channels. In addition, each channel TSV is for each die. Therefore, the plurality of terminals [F1 to F4] on the second face being coupled to different ones of the plurality of channels [each 308 is a channel].
Therefore, all applicant’s arguments are fully considered, they are not persuasive.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHAN T TRAN whose telephone number is (571)272-8709. The examiner can normally be reached MON-FRI, 9AM-5:00PM.
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/ANTHAN TRAN/Primary Examiner, Art Unit 2825
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