DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(e) the invention was described in (1) an application for patent, published under section 122(b), by another filed in the United States before the invention by the applicant for patent or (2) a patent granted on an application for patent by another filed in the United States before the invention by the applicant for patent, except that an international application filed under the treaty defined in section 351(a) shall have the effects for purposes of this subsection of an application filed in the United States only if the international application designated the United States and was published under Article 21(2) of such treaty in the English language.
Claims 18-33 are rejected under pre-AIA 35 U.S.C. 102(e) as being anticipated by Suh (US Pub. 2011/0079923).
Regarding claim 18, Fig. 1 of Suh discloses a system comprising: a processor [710, Fig. 7]; and
a plurality of stacked memory die [Die 1 to Die 4, Fig. 1] coupled to the processor;
wherein each of the stacked memory die comprises:
a substrate [110];
a first face [top] having a plurality of terminals [116, 118, 120, 122];
a second face [bottom] opposite the first face having a plurality of terminals [F1 to F4] aligned with the plurality of terminals [116, 118, 120, 122] on the first face;
a plurality of TSVs [1st column TSV to 4th column TSV] aligned with and connected to the plurality of terminals on the first face [clearly shows in Fig. 1]; and
a plurality of interconnects [the wire connections in layer 112] forming a signal path between the plurality of TSVs and respective terminals among the plurality of terminals on the second face that are not aligned [as shows in Fig. 1, the signal paths connects 116 to F4, 118 to F1, 120 to F2, and 122 to F3. They are not aligned] with the plurality of terminals on the first face [116, 118, 120, and 120] connected to respective TSVs among the plurality of TSVs.
Regarding claim 19, Fig. 7 of Suh discloses a system element [710] stacked with the plurality of stacked memory die.
Regarding claim 20, Fig. 7 of Suh discloses wherein the system element includes the processor [paragraph 0042].
Regarding claim 21, Fig. 7 of Suh discloses wherein the stacked memory die are DRAM die [paragraph 0058].
Regarding claim 22, Fig. 2 of Suh discloses wherein each of the stacked memory die further comprises a plurality of drivers [circuit 202 to drive chip select signals] connected to the plurality of interconnects.
Regarding claim 23, Fig. 2 of Suh discloses wherein the plurality of drivers are data drivers [chip ID can be considered data].
Regarding claim 24, Fig. 1 of Suh discloses wherein the plurality of terminals on the first face and the plurality of terminals on the second face are data terminals [since data are transferred between each die through the terminals, they are considered data terminals].
Regarding claim 25, Fig. 1 of Suh discloses wherein the plurality of interconnects includes a wrap around interconnect to connect a last terminal [116] on the first face with a first terminal [F4] on the second face.
Regarding claim 26, Fig. 1 of Suh discloses a first terminal at a first position [122] on the first face of each stacked memory die is connected to a second terminal [F3] at a second position on the second face of each stacked memory die; a second terminal at a second position [120] on the first face of each stacked memory die is connected to a third terminal [F2] at a third position on the second face of each stacked memory die; a third terminal at a third position [118] on the first face of each stacked memory die is connected to a fourth terminal [F1] at a fourth position on the second face of each stacked memory die; and a fourth terminal [116] at a fourth position on the first face of each stacked memory die is connected to a first terminal [F4] at a first position on the second face of each stacked memory die.
Regarding claim 27, Fig. 1 of Suh discloses wherein the plurality of stacked memory die comprise four [Die 1 to Die 4] stacked memory die [paragraph 0030].
Regarding claim 28, paragraph 0030 of Suh discloses any number of die can be stacked. Therefore, it is inherent that there can be eight stacked memory dies.
Regarding claim 29, Fig. 7 of Suh discloses wherein the processor [710] include an operating platform for executing applications, device functions or both applications and device functions [paragraph 0048].
Regarding claim 30, Fig. 7 of Suh discloses wherein the processor performs operations related to input/output or power management [as shows in Fig. 7, there are input/output devices and power supply. Therefore, operations related to input/output or power management is inherent].
Regarding claim 31, Fig. 7 of Suh discloses wherein the input/output is related to audio [SPEAKER], display [DISPLAY] or both audio and display functions.
Regarding claim 32, Fig. 7 of Suh discloses wherein the processor [710] and the plurality of stacked memory die are included in a cell phone [WIRELESS INTERFACE, MICROPHONE].
Regarding claim 33, Fig. 7 of Suh discloses wherein processing operations performed by the processor include the execution of an operating platform or operating system on which applications, device functions, or both are executed [paragraph 0048].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHAN T TRAN whose telephone number is (571)272-8709. The examiner can normally be reached MON-FRI, 9AM-5:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached at 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ANTHAN TRAN/Primary Examiner, Art Unit 2825