DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-8, 10, 23-24 and 29-42 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-8 and 10-20 of U.S. Patent No. 12,074,108. Although the claims at issue are not identical, they are not patentably distinct from each other because of the followings:
Although the conflicting claims are not identical, the scope of the claimed limitations of the instant application as claimed in claims 1-8, 10, 23-24 and 29-42 is similar to that of the claimed limitations of U.S. Patent No. 12,074,108 as claimed in claims 1-8 and 10-20. Therefore, the claims are not patentably distinct from each other.
The instant application:
1. A semiconductor device comprising: a first wiring layer at a first layer level over a substrate, the first wiring layer including: a plurality of first wirings extending in a first direction; and a second wiring extending in the first direction, the second wiring having a rectangular loop, a first side of the rectangular loop facing one of the plurality of first wirings, and the first side of the rectangular loop being at a predetermined distance from the one of the plurality of first wirings; and a gate electrode layer at a second layer level different from the first layer level, the gate electrode layer including a gate electrode of a transistor.
2. The semiconductor device according to claim 1, wherein a width of the second wiring is 200 nm or less.
41. The semiconductor device according to claim 1, wherein the predetermined distance is 200 nm or less.
42. The semiconductor device according to claim 1, wherein a width of the second wiring is 200 nm or less and the predetermined distance is 200 nm or less.
3. The semiconductor device according to claim 1, wherein each side of the rectangular loop has a length of 500 nm or greater.
4. The semiconductor device according to claim 1, wherein a first side of the rectangular loops is parallel to the first direction.
5. The semiconductor device according to claim 1, wherein the predetermined distance is approximately equal to a width of the second wiring.
6. The semiconductor device according to claim 1, wherein the width of second wiring is constant in the loop.
7. The semiconductor device according to claim 1, further comprising: a contact formed on one side of the rectangular loop.
8. The semiconductor device according to claim 7, further comprising: a second wiring layer at a third layer level different from the first layer level and the second layer level, the second wiring layer including a third wiring, wherein the contact is formed to electrically connect the second wiring to the third wiring.
10. The semiconductor device according to claim 8, wherein a width of the first wiring is different from a width of the third wiring.
23. The semiconductor device according to claim 1, wherein the plurality of first wirings and the second wiring are formed by reactive ion etching.
24. The semiconductor device according to claim 1, wherein the rectangular loop has a second side that is contiguous with and extends in a second direction crossing the first direction from a main body of the second wiring, the first side that is contiguous with the second side, a third side that is contiguous with the first side and parallel to the second side, and a fourth side that is contiguous with the third side and the second side, parallel to the first side, and included in the main body.
29. The semiconductor device according to claim 1, wherein one of the first wiring and the second wiring is a signal line.
30. The semiconductor device according to claim 1, wherein a width of the first wiring is approximately equal to a width of the second wiring.
31. The semiconductor device according to claim 1, further comprising: a plurality of memory pillars provided between the first wiring layer and the substrate, and extending in a third direction crossing the first direction.
32. The semiconductor device according to claim 31, wherein each of the plurality of memory pillars includes a charge storage film.
33. The semiconductor device according to claim 31, wherein each of the plurality of memory pillars includes a semiconductor film and a charge storage film.
34. The semiconductor device according to claim 1, further comprising: a third wiring layer provided between the first wiring layer and the substrate, the third wiring layer including a bit line.
35. The semiconductor device according to claim 34, further comprising: a fourth wiring layer including a word line, the third wiring layer being provided between the first wiring layer and the fourth wiring layer.
36. The semiconductor device according to claim 1, further comprising: a fourth wiring layer provided between the first wiring layer and the substrate, the fourth wiring layer including a word line.
37. The semiconductor device according to claim 1, wherein the first wiring layer includes a sixth wiring for connecting a memory cell array and a peripheral circuit.
38. The semiconductor device according to claim 1, further comprising: a bit line extending in a second direction crossing the first direction.
39. The semiconductor device according to claim 1, further comprising: a word line extending in the first direction.
40. The semiconductor device according to claim 1, wherein the semiconductor device receives a write enable signal.
U.S. Patent No. 12,074,108:
1. A semiconductor device comprising: a first wiring layer at a first layer level over a substrate, the first wiring layer including: a first wiring extending in a first direction; and a second wiring extending in a second direction crossing the first direction, the second wiring having an end that is formed into one or more rectangular loops, a first side of the rectangular loops facing the first wiring, and the first side of the rectangular loops being at a predetermined distance away from the first wiring; and a gate electrode layer at a second layer level different from the first wiring layer, the gate electrode layer including a gate of a transistor on the substrate.
2. The semiconductor device according to claim 1, wherein a width of the second wiring is 200 nm or less
3. The semiconductor device according to claim 1, wherein the first side of the one or more rectangular loops has a length of 500 nm or greater.
4. The semiconductor device according to claim 1, wherein the first side of the one or more rectangular loops is parallel to the first direction.
5. The semiconductor device according to claim 1, wherein the predetermined distance is approximately equal to a width of the second wiring.
6. The semiconductor device according to claim 1, wherein the width of second wiring is constant in the loop.
7. The semiconductor device according to claim 1, wherein the end of the second wiring is formed into one rectangular loop having a second side that is contiguous with and extends in the second direction from a main body of the second wiring, the first side, which is contiguous with the second side, a third side that is contiguous with the first side and parallel to the second side, and a fourth side that is contiguous with the third side and the second side and parallel to the first side.
9. The semiconductor device according to claim 1, further comprising: a second wiring layer including a third wiring; and a contact formed at an end of the second wiring and electrically connecting the second wiring to the third wiring, wherein a width of the first wiring is different from a width of the third wiring.
8. The semiconductor device according to claim 1, wherein the first wiring and the second wiring are formed by reactive ion etching.
7. The semiconductor device according to claim 1, wherein the end of the second wiring is formed into one rectangular loop having a second side that is contiguous with and extends in the second direction from a main body of the second wiring, the first side, which is contiguous with the second side, a third side that is contiguous with the first side and parallel to the second side, and a fourth side that is contiguous with the third side and the second side and parallel to the first side.
11. The semiconductor device according to claim 1, wherein one of the first wiring and the second wiring is a signal line.
12. The semiconductor device according to claim 1, wherein a width of the first wiring is approximately equal to a width of the second wiring.
13. The semiconductor device according to claim 1, further comprising: a plurality of memory pillars between the first wiring layer and the substrate, each of the plurality of memory pillars extending in a third direction crossing the first direction and the second direction.
14. The semiconductor device according to claim 13, wherein each of the plurality of memory pillars includes a charge storage film, a tunnel insulating film, and a semiconductor material.
15. The semiconductor device according to claim 1, further comprising: a third wiring layer formed between the first wiring layer and the substrate, wherein the third wiring layer includes a bit line.
16. The semiconductor device according to claim 15, further comprising: a fourth wiring layer, the third wiring layer formed between the first wiring layer and the fourth wiring layer, wherein the fourth wiring layer includes a word line.
17. The semiconductor device according to claim 1, wherein the first wiring layer includes a sixth wiring for connecting a memory cell array and a peripheral circuit.
18. The semiconductor device according to claim 1, further comprising: a bit line extending in the first direction.
19. The semiconductor device according to claim 1, further comprising: a word line extending in the second direction.
20. The semiconductor device according to claim 1, wherein the semiconductor device receives a write enable signal.
Allowable Subject Matter
Claims 9, 11-22, 25-28 and 43 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure Cicalo et al. (US 2014/0332979) disclose semiconductor device the included wiring structure having plurality of interconnect layers formed over semiconductor substrate.
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BROOK KEBEDE whose telephone number is 571-272-1862. The examiner can normally be reached Monday Friday 8:00 AM 5:00 PM.
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/BROOK KEBEDE/
Primary Examiner, Art Unit 2894
/BK/
August 22, 2026
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