DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
For Examiner’s Interview fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html).
Status of claim(s) to be treated in this office action:
Independent: 1, 7, and 17.
Pending: 1-20.
Information Disclosure Statement
Applicant’s IDS(s) submitted on 7/22/2024 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has/have considered by the examiner and made of record.
Specification
The disclosure is objected to because of the following informalities:
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR INTERCONNECT STRUCTURE WITH SELECTIVE AIR GAPS.
Drawings
The drawings are objected to because as shown in figure 4A, 318 is an opening not a layer so on figure 4B a top view should show 320, in figure 5B a top view should show 330 in between 332, in figure 6B 320 should be between 332, in figure 7B should show 310 and part of 312, in figure 8B should be cover with 336, in figure 10B area 334 should show 338 and in between 338 is layer 336, in figure 11B and 12B 342 should show in the white area. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 17 and 19 is/are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Chen et al., US PG pub. 20170194191 A1.
Re: Independent Claim 17, Chen discloses a dielectric layer (100, fig. 4A-4B);
a conductive layer (120 and 160, fig. 4A-4B) disposed on the dielectric layer (100, fig. 4A-4B), wherein the conductive layer (120 and 160, fig. 4A-4B) comprises a line portion (120, fig. 4A-4B) and a via portion (160, fig. 4A-4B) extending upward from the line portion (120, fig. 4A-4B);
a conductive line (120, fig. 4A-4B) disposed on the dielectric layer (100, fig. 4A-4B), wherein the conductive line (120, fig. 4A-4B) is disposed adjacent the line portion (120, fig. 4A-4B) of the conductive layer (120 and 160, fig. 4A-4B);
a continuous layer (114, fig. 3A-4B) disposed on and in contact with a side surface of the via portion (160, fig. 4A-4B), a side surface of the line portion (120, fig. 3B), a top surface of the dielectric layer (100, fig. 4A-4B), side surfaces of the conductive line (120, fig. 4A-4B), and a top surface of the conductive layer (120 and 160, fig. 4A-4B); and
a dielectric material (116, fig. 3B-3C) disposed between the conductive layer (120 and 160, fig. 4A-4B) and the conductive line (120, fig. 4A-4B), wherein an air gap (150, fig. 3A-4B) is formed below the dielectric material (116, fig. 3C).
Re: Claim 19, Chen disclose(s) all the limitations of claim 17 on which this claim depends. Chen further discloses: wherein the air gap (150, fig. 3A-4B) is defined by portions of the continuous layer (114, fig. 3A-4B) and the dielectric material (116, fig. 3B-3C).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Chen et al., US PG pub. 20170194191 A1; in view of Lin et al., US Patent 10457548 B2.
Re: Independent Claim 1, Chen discloses a plurality of conductive line (120, fig. 4A-4B)s disposed over a dielectric layer (100, fig. 4A-4B), wherein air gap (150, fig. 3A-4B)s are located between adjacent conductive line (120, fig. 4A-4B)s of the plurality of conductive line (120, fig. 4A-4B)s, and each air gap (150, fig. 3A-4B) has a height substantially the same as a height of each conductive line (120, fig. 4A-4B);
a conductive via (160, fig. 4B) extending upward from one of the plurality of conductive line (120, fig. 4A-4B)s, wherein the one conductive line (120, fig. 4A-4B) and the conductive via (160, fig. 4B); and
a first dielectric material (116, fig. 3A-4B) disposed over the plurality of conductive line (120, fig. 4A-4B)s, wherein the first dielectric material (116, fig. 3A-4B) surrounds the conductive via (160, fig. 4B).
Chen is silent regarding: conductive line (120, fig. 4A-4B) and the conductive via (160, fig. 4B) are monolithic and have substantially the same grain size.
Lin teaches the conductive line (108, fig. 1E) and conductive via (112,fig. 1E) are monolithic and have substantially the same grain size (since 108 and 112 is made use identical deposition parameters therefore 108 and 112 would have the same grain size).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include the conductive line and via as a monolithic structure this can improve electrical performance by having no discontinuity in conductivity between via and line and would reduce contact resistance and minimizes parasitic effect.
Re: Claim 2, Chen and Lin discloses all the limitations of claim 1 on which this claim depends. Chen further discloses: a layer (114, fig. 3B) disposed between the conductive via (160, fig. 4B) and the first dielectric material (116, fig. 3A-4B) and between the plurality of conductive line (120, fig. 4A-4B)s and the first dielectric material (116, fig. 3A-4B).
Re: Claim 3, Chen and Lin discloses all the limitations of claim 2 on which this claim depends. Chen further discloses: wherein each air gap (150, fig. 3A-4B) is defined by the layer (114, fig. 3B) and the first dielectric material (116, fig. 3A-4B).
Claim(s) 4-6 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Chen et al., US PG pub. 20170194191 A1; in view of Lin et al., US Patent 10457548 B2; further in view of Tung et al., US PG pub. 20160240428 A1.
Re: Claim 4, Chen and Lin discloses all the limitations of claim 2 on which this claim depends. Chen and Lin is silent regarding: a second dielectric material disposed over the conductive via (160, fig. 4B) and the first dielectric material (116, fig. 3A-4B).
Tung discloses a second dielectric material (240, fig. 21) disposed over the conductive via (210b, fig. 21) and the first dielectric material (204, fig. 21).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include formed a stacked conductive via or buried vias above existing via structure this allow high-density interconnect designs to navigate thick multi-layer boards without requiring a single large through hole which can saves routing space.
Re: Claim 5, Chen and Lin discloses all the limitations of claim 4 on which this claim depends. Chen and Lin is silent regarding: a conductive material disposed in the second dielectric material, wherein the conductive material is disposed over the conductive via (160, fig. 4B).
Tung discloses a conductive material (1105, fig. 21) disposed in the second dielectric material (240, fig. 21), wherein the conductive material (1105, fig. 21) is disposed over the conductive via (210b, fig. 21).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include formed a stacked conductive via or buried vias above existing via structure this allow high-density interconnect designs to navigate thick multi-layer boards without requiring a single large through hole which can saves routing space.
Re: Claim 6, Chen and Lin discloses all the limitations of claim 5 on which this claim depends. Chen and Lin is silent regarding: wherein the conductive material is in contact with the conductive via (160, fig. 4B).
Tung discloses wherein the conductive material (1105, fig. 21) is in contact with the conductive via (210b, fig. 21).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include formed a stacked conductive via or buried vias above existing via structure this allow high-density interconnect designs to navigate thick multi-layer boards without requiring a single large through hole which can saves routing space.
Claim(s) 7-12 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Chen et al., US PG pub. 20170194191 A1; in view of Lin et al., US Patent 10457548 B2; further in view of Lee et al., US PG pub. 20220199522 A1.
Re: Independent Claim 7, Chen discloses a conductive layer (120 and 160, fig. 4A-4B) comprising a line portion (120, fig. 4A-4B) and a via portion (160, fig. 4A-4B) extending upward from the line portion (120, fig. 4A-4B),
a conductive line (120, fig. 4A-4B) disposed adjacent the line portion (120, fig. 4A-4B) of the conductive layer (120 and 160, fig. 4A-4B), wherein an air gap (150, fig. 3A-4B) is formed between the conductive line (120, fig. 4A-4B) and the line portion (120, fig. 4A-4B) of the conductive layer (120 and 160, fig. 4A-4B) and
a first dielectric material (116, fig. 3A-4B) disposed over the air gap (150, fig. 3A-4B) and between the line portion (120, fig. 4A-4B) of the conductive layer (120 and 160, fig. 4A-4B) and the conductive line (120, fig. 4A-4B).
Chen is silent regarding: wherein the line portion (120, fig. 4A-4B) and the via portion (160, fig. 4A-4B) are monolithic and have substantially the same grain size.
Lin teaches the conductive line (108, fig. 1E) and conductive via (112,fig. 1E) are monolithic and have substantially the same grain size (since 108 and 112 is made use identical deposition parameters therefore 108 and 112 would have the same grain size).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include the conductive line and via as a monolithic structure this can improve electrical performance by having no discontinuity in conductivity between via and line and would reduce contact resistance and minimizes parasitic effect.
Chen and Lin is silent regarding: a height of the air gap is less than a height of the conductive line.
Lee teach an air gap (AG, fig. 3) height is less than height of the conductive line (LIL1, fig. 3).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include air gap smaller than conductive line since this can improve lower parasitic capacitance, an air gap bigger than metal wires can also decrease parasitic capacitance however the bigger air gap could decrease heat dissipation and cause mechanical weakness.
Re: Claim 8, Chen and Lin discloses all the limitations of claim 7 on which this claim depends. Chen further discloses: a continuous layer (114, fig. 3A-4B) disposed between the via portion (160, fig. 4A-4B) and the first dielectric material (116, fig. 3A-4B), between the line portion (120, fig. 4A-4B) and the first dielectric material (116, fig. 3A-4B), and between the line portion (120, fig. 4A-4B) and the air gap (150, fig. 3A-4B), wherein the continuous layer (114, fig. 3A-4B) covers side surfaces and a top surface of the conductive line (120, fig. 4A-4B).
Re: Claim 9, Chen and Lin discloses all the limitations of claim 8 on which this claim depends. Chen further discloses: a dielectric layer (100, fig. 4A-4B), wherein the conductive line (120, fig. 4A-4B) and the conductive layer (120 and 160, fig. 4A-4B) are disposed on the dielectric layer (100, fig. 4A-4B).
Re: Claim 10, Chen and Lin discloses all the limitations of claim 9 on which this claim depends. Chen further discloses: wherein the continuous layer (114, fig. 3A-4B) is disposed on the dielectric layer (100, fig. 4A-4B).
Re: Claim 11, Chen and Lin discloses all the limitations of claim 10 on which this claim depends. Chen and Lin is silent regarding: wherein the continuous layer comprises a metal oxide or oxide doped carbide.
Lee teaches wherein the continuous layer (ESL, fig. 3) comprises a metal oxide (¶0076).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include metal oxide for the continuous layer since metal oxide can prevent over-etching and electromigration.
Re: Claim 12, Chen and Lin discloses all the limitations of claim 7 on which this claim depends. Chen and Lin is silent regarding: etch stop layer disposed on and in contact with the first dielectric material (116, fig. 3A-4B).
Lee teaches a etch stop layer (ESL, fig. 3) disposed on and in contact with the dielectric material (DOD, fig. 3).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a etch stop layer on the dielectric material since etch stop layer can protect underlying layers from over etching damage.
Claim(s) 20 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Chen et al., US PG pub. 20170194191 A1; in view of Lee et al., US PG pub. 20220199522 A1.
Re: Claim 20, Chen discloses all the limitations of claim 17 on which this claim depends.
Chen is silent regarding: wherein the continuous layer (114, fig. 3A-4B) comprises a metal oxide or oxide doped carbide.
Lee teaches wherein the continuous layer (ESL, fig. 3) comprises a metal oxide (¶0076).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include metal oxide for the continuous layer since metal oxide can prevent over-etching and electromigration.
Prior art made of record and not relied upon are considered pertinent to current application disclosure.
* (“Yang et al., US PG pub. 20160020176 A1”) Discloses a device includes a first conductive line in a first metallization layer over a dielectric layer, wherein the first conductive line is wrapped by a first polymer layer on three sides and the first conductive line and the dielectric layer are separated by a bottom portion of the first polymer layer, a second conductive line over the dielectric layer, wherein the second conductive line is wrapped by a second polymer layer on three sides and the second conductive line and the dielectric layer are separated by a bottom portion of the second polymer layer and an air gap between the first conductive line and the second conductive line.
* (“Rha et al., US PG pub. 20150287676 A1”) discloses a semiconductor device includes a substrate, a plurality of first conductive patterns disposed on the substrate and a plurality of second conductive patterns disposed on the first conductive patterns. Respective air gaps are disposed between adjacent ones of the first conductive patterns overlying a first region of the substrate, while adjacent ones of the first conductive patterns overlying a second region of the substrate do not have air gaps disposed therebetween. The air gaps may include first air gaps, and the device may further include second air gaps disposed between adjacent ones of the second conductive patterns in the second region. Adjacent ones of the second conductive patterns overlying a second region of the substrate may not have air gaps disposed therebetween.
* (“Xie et al., US Patent 11171044 B1”) discloses a semiconductor device includes selectively etching one or more of a plurality of conductive layers within a metallization level to obtain one or more recessed conductive layers each corresponding to a conductive line lacking a via disposed thereon and at least one conductive line having a via disposed thereon. The metallization level is disposed on a base structure including one or more underlying devices. The method further includes forming a pair of planarization stop layers on each of the one or more recessed conductive layers to a height of the via, and forming a plurality of interlevel dielectric (ILD) layers having a uniform height across the metallization level using the one or more pairs of planarization stop layers.
Allowable Subject Matter
Claim(s) 13 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Re: Claim 13 (and its dependent claim(s) 14-16), the prior art of record do not disclose or suggest, in combination with all other limitations in the claim: a second dielectric material disposed on and in contact with the via portion of the conductive layer and the etch stop layer.
Re: Claim 18, the prior art of record do not disclose or suggest, in combination with all other limitations in the claim: wherein a top surface of the via portion of the conductive layer and a top surface of the dielectric material are coplanar.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TSZ CHIU whose telephone number is 571-272-8656. The examiner can normally be reached on M-F, 9:00AM to 5:00PM (EST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached on 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TSZ K CHIU/Examiner, Art Unit 2898 Tsz.Chiu@uspto.gov
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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