DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Regarding claim 9, the claim recites “above the first conductive pad” and “on the second conductive pad” in lines 3 and 4, respectively, of the claim. This is inconsistent with Fig. 1 of the drawings and paragraphs 0063-0064 of the specification, thus rendering the claim indefinite. It is suggested that “first” and “second” in lines 3-4 are switched to provide clarity.
Regarding claim 11, the claim recites “between the first conductive pad…” in line 2 of the claim. This is inconsistent with Fig. 1 of the drawings and paragraphs 0063-0064 of the specification, thus rendering the claim indefinite. It is suggested that “first” be switched to “second” to provide clarity.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, and 9-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jin et al. (2021/0398908, hereafter Jin).
Regarding claim 1, Jin discloses a semiconductor package comprising: a redistribution line structure (110, Fig. 1); a semiconductor chip (120, Fig. 1) on a first surface of the redistribution line structure; an under-bump structure (170/180, Fig. 1) on a second surface of the redistribution line structure that is opposite the first surface, the under-bump structure including a passivation layer (170, Fig. 1) and a conductive pattern layer (180, Fig. 1); an electronic component (210, Fig. 1, par. 0085) above the under-bump structure; and an underfill member (200, Fig. 1) filling a space between the under-bump structure and the electronic component, wherein the conductive pattern layer is spaced apart from one side surface of the electronic component in plan view (Fig. 1), and the conductive pattern layer including a bleeding prevention pattern, the bleeding prevention pattern including at least one dam region (171/172, Fig. 13) configured to block bleeding of the underfill member from the one side surface of the electronic component (par. 0133), and the passivation layer defining at least one trench therein adjacent to the at least one dam region (T1, Fig. 13, par. 0074).
Regarding claim 2, Jin discloses a semiconductor package wherein the at least one dam region includes a plurality of dam regions (171/172) spaced apart from each other in a direction away from the one side surface of the electronic component (Fig. 13), and the at least one trench is a single trench (T, par. 0096) including regions respectively positioned between the plurality of dam regions (T1_1/T1_2/T1_3, Fig. 13).
Regarding claim 9, Jin discloses a semiconductor package wherein the conductive pattern layer (180) further includes a first conductive pad (182) and a second conductive pad (192), the electronic component is above the [second] conductive pad (192), and the semiconductor package further comprises a first conductive bump (185) on the [first] conductive pad (182) (Fig. 1).
Regarding claim 10, Jin discloses a semiconductor package wherein the first conductive pad (182, Fig. 1), the second conductive pad (192, Fig. 1), and the bleeding prevention pattern (171/172/T1, Fig. 13) are at a same level on the passivation layer (170, Fig. 1, 13).
Regarding claim 11, Jin discloses a semiconductor package further comprising a second conductive bump (195) between the [second] conductive pad (192) and the electronic component (210), the second conductive bump being covered with the underfill member (200) (Fig. 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Jin.
Regarding claim 13, Jin, discussed above, fails to specifically disclose a semiconductor package wherein the electronic component is an integrated stacked capacitor (ISC).
However, Jin teaches a semiconductor package wherein the electronic component is an integrated stacked capacitor (ISC) (par. 0085).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Jin by providing an integrated stacked capacitor in order to maximize capacitance per unit area by extending vertically, saving space while providing decoupling near circuitry.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Jin in view of Myung et al. (2020/0168565, hereafter Myung).
Regarding claim 3, Jin, discussed above, fails to disclose a semiconductor package wherein the at least one dam region includes a plurality of dam regions spaced apart from each other in a direction away from the one side surface of the electronic component, and the at least one trench comprises a plurality of trenches respectively positioned between the plurality of dam regions.
However, Myung teaches a semiconductor package wherein the at least one dam region includes a plurality of dam regions (126, Fig. 12) spaced apart from each other in a direction away from the one side surface of the electronic component (120, Fig. 9), and the at least one trench comprises a plurality of trenches (124) respectively positioned between the plurality of dam regions (Fig. 12).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Jin with Myung by providing a plurality of trenches between a plurality of dams in order to create a series of barriers that drop liquid’s momentum and trap overflow.
Claims 4, 6, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Jin in view of Yim et al. (2011/0275177, hereafter Yim) and Tseng et al. (2022/0278067, hereafter Tseng).
Regarding claim 4, Jin, discussed above, fails to disclose a semiconductor package of claim 1, wherein the at least one dam region comprises a plurality of dam regions, and the plurality of dam regions includes a first dam region closest to the electronic component from among the plurality of dam regions.
However, Yim teaches semiconductor package wherein the at least one dam region comprises a plurality of dam regions (280a, Fig. 2A), and the plurality of dam regions includes a first dam region (280a inner, Fig. 2A) closest to the electronic component (200, Fig. 2A) from among the plurality of dam regions.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Jin with Yim by providing a dam closest to the component in order to act as primary barrier while subsequent dams provide redundant spill protection.
Further, Jin and Yim fail to disclose the passivation layer including a region exposed through the bleeding prevention pattern, the region of the passivation layer extending from a region adjacent to the one side surface of the electronic component to a trench of the at least one trench that is adjacent to the first dam region in plan view.
However, Tseng teaches the passivation layer (disclosed by Jin) including a region exposed (DL1, Fig. 4D; OP1, Fig. 5D) through the bleeding prevention pattern (29, Fig. 5D), the region of the passivation layer extending from a region adjacent to the one side surface of the electronic component (CR, Fig. 4D, 5D) to a trench (27c, Fig. 4D) of the at least one trench that is adjacent to the first dam region in plan view.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Jin and Yim with Tseng by providing an exposed region through the bleeding prevention layer in order to control flow by relieving pressure and allowing underfill to pass through in capture points, preventing uncontained flow.
Regarding claim 6, Jin fails to disclose a semiconductor package wherein a length of the trench of the at least one trench between the plurality of dam regions is 1 µm or more and 10 µm or less, and the length being along a direction toward the plurality of dam regions from the one side surface of the electronic component.
However, Yim teaches the length being along a direction toward the plurality of dam regions from the one side surface of the electronic component. Further, capillary action at small distance values may be too strong, thus pulling the underfill through and over the bleeding prevention pattern. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Regarding claim 17, Jin fails to disclose a semiconductor package wherein the plurality of dam regions includes a first dam region closest to the electronic component from among the plurality of dam regions.
However, Yim teaches a semiconductor package wherein the plurality of dam regions includes a first dam region (280a inner) closest to the electronic component (200) from among the plurality of dam regions (280a) (Fig. 2A).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Jin with Yim by providing a dam closest to the electronic component in order to act as primary barrier while subsequent dams provide redundant spill protection.
Further, Jin and Yim fail to disclose the passivation layer including a region exposed through the bleeding prevention pattern, the region of the passivation layer extending from a region adjacent to the one side surface of the electronic component to a trench of the at least one trench that is adjacent to the first dam region in plan view.
However, Tseng teaches the passivation layer (disclosed by Jin) including a region exposed (DL1, Fig. 4D; OP1, Fig. 5D), through the bleeding prevention pattern (29, Fig. 5D), the region of the passivation layer extending from a region adjacent to the one side surface of the electronic component (CR, Fig. 4D, 5D) to a trench of the at least one trench (27c, Fig. 4D) that is adjacent to the first dam region in plan view.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Jin and Yim with Tseng by providing an exposed region through the bleeding prevention layer in order to control flow by relieving pressure and allowing underfill to pass through in capture points, preventing uncontained flow.
Claim 16 are rejected under 35 U.S.C. 103 as being unpatentable over Jin in view of Yim and Myung.
Regarding claim 16, Jin and Yim, discussed above, fail to disclose a semiconductor package wherein the at least one trench comprises a plurality of trenches respectively positioned between the plurality of dam regions.
However, Myung teaches a semiconductor package wherein the at least one trench comprises a plurality of trenches (124, Fig. 12) respectively positioned between the plurality of dam regions (126, Fig. 12).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Jin and Yim with Myung by providing trenches between dams in order to create a series of barriers that drop liquid’s momentum and trap overflow.
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Jin in view of Lee et al. (2011/0260338, hereafter Lee).
Regarding claim 7, Jin, discussed above, fails to disclose a semiconductor package wherein a depth of the at least one trench is 1 µm or more and 10 µm or less.
However, Lee teaches a semiconductor package wherein a depth of the at least one trench (160) is 1 µm or more and 10 µm or less (par. 0044).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Jin with Lee by providing a trench depth of 1 to 10 microns in order to balance capillary pinning force required to arrest liquid, preventing flow without excessive structural limits.
Regarding claim 8, Jin fails to disclose a semiconductor package wherein a thickness of the bleeding prevention pattern is 1 µm or more and 15 µm or less.
However, Lee teaches a semiconductor package wherein a thickness of the bleeding prevention pattern (164) is 1 µm or more and 15 µm or less (par. 0044).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Jin with Lee by providing a trench depth of 1 to 10 microns in order to balance capillary pinning force required to arrest liquid, preventing flow without excessive structural limits.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Jin in view of Park et al. (2023/0060115, hereafter Park).
Regarding claim 12, Jin, discussed above, fails to disclose a semiconductor package wherein the bleeding prevention pattern includes a first metal layer, and a second metal layer on the first metal layer.
However, Park teaches a semiconductor package wherein the bleeding prevention pattern (500, Fig. 1B) includes a first metal layer (501, Fig. 1B), and a second metal layer (502, Fig. 1B) on the first metal layer (par. 0038).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Jin with Park by providing a bleeding prevention pattern with first and second metal layers in order to provide adhesion and conductive surface while building the structural height
Claims 5, 14, 15, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Jin in view of Yim.
Regarding claim 5, Jin, discussed above, fails to disclose a semiconductor package wherein a length of a dam region of the at least one dam region is 1 µm or more and 10 µm or less, and the length being along a direction toward the dam region from the one side surface of the electronic component.
However, Yim teaches the length being along a direction toward the dam region from the one side surface of the electronic component. Further, capillary action at small value distances may be too strong, thus pulling the underfill through and over the bleeding prevention pattern. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Regarding claim 14, Jin discloses semiconductor package comprising: a redistribution line structure (110, Fig. 1); a semiconductor chip (120, Fig. 1) on a first surface of the redistribution line structure; an under-bump structure (170/180, Fig. 1) on a second surface of the redistribution line structure opposite the first surface, the under-bump structure including a passivation layer (170, Fig. 1) and a conductive pattern layer (180, Fig. 1); an electronic component (210, Fig. 1) above the under-bump structure; and an underfill member (200, Fig. 1) filling a space between the under-bump structure and the electronic component, and the passivation layer (170) defines at least one trench therein between the plurality of dam regions (Fig. 9-10. Par. 0074).
Jin fails to disclose the conductive pattern layer includes a bleeding prevention pattern surrounding the electronic component, the bleeding prevention pattern including a plurality of dam regions spaced apart from each other along a direction extending away from one side surface of the electronic component in plan view, and wherein the plurality of dam regions are at a region adjacent the one side surface of the electronic component, the plurality of dam regions are configured to block bleeding of the underfill member from the one side surface of the electronic component.
However, Yim teaches the conductive pattern layer includes a bleeding prevention pattern (280, par. 0033) surrounding the electronic component (200, Fig. 2A), the bleeding prevention pattern including a plurality of dam regions (280a, Fig. 2A) spaced apart from each other along a direction extending away from one side surface of the electronic component in plan view, and wherein the plurality of dam regions are at a region adjacent the one side surface of the electronic component (280a right/left), the plurality of dam regions are configured to block bleeding of the underfill member from the one side surface of the electronic component (par. 0033).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Jin with Yim by providing a bleeding prevention pattern surrounding the component with dams on the side in order to act as primary barrier while subsequent dams provide redundant spill protection.
Regarding claim 15, Jin discloses a semiconductor package wherein the at least one trench is a single trench (T, par. 0096) including regions (T1_1/T1_2/T1_3, Fig. 13) respectively positioned between the plurality of dam regions (171/172, Fig. 13).
Regarding claim 18, Jin discloses semiconductor package comprising: a redistribution line structure (110, Fig. 1); a semiconductor chip (120, Fig. 1) on a first surface of the redistribution line structure; an under-bump structure (170/180, Fig. 1) on a second surface of the redistribution line structure that is opposite the first surface, the under-bump structure including a passivation layer (170, Fig. 1) and a conductive pattern layer (180, Fig. 1), the conductive pattern layer including a bleeding prevention pattern (T1/T2/T3/171/172, Fig. 13), at least one first conductive pad (192, Fig. 1), and second conductive pads (182, Fig. 1); an electronic component (210, Fig. 1) above the at least one first conductive pad; an underfill member (200, Fig. 1) filling a space between the at least one first conductive pad and the electronic component; and conductive bumps (185, Fig. 1) on the second conductive pads, wherein the bleeding prevention pattern is at a region adjacent to one side surface of the electronic component (Fig. 13), and the passivation layer defines a trench therein adjacent to the bleeding prevention pattern in plan view (par. 0074).
Jin fails to disclose the second conductive pads are at regions adjacent to remaining side surfaces of the electronic component other than the one side surface.
However, Yim teaches the second conductive pads (115) are at regions adjacent to remaining side surfaces of the electronic component (200) other than the one side surface (Fig. 2A).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Jin with Yim by providing conductive pads around the component in order to provide multiple electrical connection points while acting as grounding contacts.
Regarding claim 19, Jin discloses a semiconductor package wherein the bleeding prevention pattern includes at least one dam region (171/172, Fig. 13) configured to block bleeding of the underfill member from the one side surface of the electronic component (par. 0133), and the trench is adjacent to the at least one dam region (T1, Fig. 13).
Regarding claim 20, Jin discloses a semiconductor package wherein the at least one first conductive pad (192), the second conductive pads (182), and the bleeding prevention pattern (171/172) are at a same level on the passivation layer (Fig. 1, 14).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLES M BRECHT whose telephone number is (571)272-9634. The examiner can normally be reached Mon-Fri: 7:30am - 5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at (572) 272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.M.B./ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
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