Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment of Amendment
Acknowledgment is made of applicant's amendment, filed on 2/16/2026. The changes and remarks disclosed therein have been considered. Claim 7 has been cancelled by the amendment. Claims 1, 8, 15 have been amended. Therefore, claims 1-6, 8-17 remain pending in the application.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 8 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 8 recites dependency from claim 7, which has been cancelled. A dependent claim must refer to a previous claim that exists. Proper correction is required.
Response to Arguments
Applicant's arguments have been fully considered but they are not persuasive.
Applicant amended the independent claims 1, 15 with additional limitation: “a transition of the second control signal defines completion of the read operation and simultaneously defines initiation of the write operation”, and argues that prior art does not teach this limitation. In particular, applicant argues “Schreiber's read and write cycles are inherently sequential and separately triggered events”, and concludes: “Schreiber does not disclose a control architecture where a single transition of an internal control signal simultaneously defines both an end of a read operation and a start of a write operation. More particularly, Schreiber fails to disclose that "a transition of the second control signal defines completion of the read operation and simultaneously defines initiation of the write operation," as required by amended claim 1”.
Examiner respectfully disagrees.
The newly added limitation only requires “a transition of the second control signal defines completion of the read operation and simultaneously defines initiation of the write operation”, it does not require the same physical signal line simultaneously trigger both circuits. Under Broadest reasonable interpretation, the limitation merely requires that a transition of the second control signal marks the boundary between completion of a read operation and initiation of a write operation. It only requires a control signal transition defines the change of operation mode.
Moreover, claim 1 does not require that the read and write operations occurs truly simultaneously. Rather the claims only requires that the transition of the control signal define the boundary between two operations.
SCHREIBER teaches that the access control logic configures pulse generator 212 to generate pulses corresponding to read duty cycles or write duty cycles depending on the operational mode of the memory ([0023]-[0025]). When the control logic transitions the configuration of the pulse generator from the read cycle to the write cycle, the read operation is completed and the write operation begins. Accordingly, the transition of the duty-cycle control configuration defines completion of the read operation and initiation of the write operation.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 8-10, 13-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by SCHREIBER PG PUB 20120147682 (hereinafter SCHREIBER).
Regarding independent claim 1, SCHREIBER teaches a storage device (figure 2) comprising:
core circuitry comprising one or more bitcells (204 in figure 2, [0021], “…the SRAM array 204…”), each bitcell accessible via a corresponding bitline (“bit lines indicated in [0021], “…SRAM array 204 includes column select circuitry configured to select or otherwise enable access to (e.g., writing to and/or reading from) a particular column of cells within the SRAM array 204 by coupling the bit line(s) of a selected column to the access circuitry 206, 208 in response to signals from the control module 202…”) and wordline (“word line” indicated in [0021], “…the control module 202 asserts a word line select signal for a particular row of the SRAM array 204 that includes an addressed SRAM cell (e.g., the SRAM cell to be accessed)…”);
column selection circuitry (“column select circuitry” in [0022]) to, responsive to a column select signal (“column select signal” in [0022], “…access control logic 210 concurrently asserts or otherwise provides a column select signal to the column select circuitry of the SRAM array 204 to couple the bit line(s) associated with the addressed SRAM cell to the appropriate access circuitry 206, 208, thereby enabling access to the addressed SRAM cell…”), select at least one bitcell via one or more bitlines;
wordline selection circuitry to, responsive to a wordline select signal (“wordline select signal” in [0020], “…the control module 202 asserts a word line select signal for a particular row of the SRAM array 204 that includes an addressed SRAM cell (e.g., the SRAM cell to be accessed)…”), select the at least one bitcell via one or more wordlines;
control circuitry (202 in figure 2) to, in a first mode of operation (SCHREIBER teaches various read/write duty cycle configurations):
provide a first wordline select signal to the wordline selection circuitry responsive to a first control signal (SCHREIBER teaches asserting a WL select signal via pulse generator 212 under control of access control logic 210, [0021]-[0023], “first control signal” has been interpreted as read or write instructions in [0027], “..memory controller 108 may provides instructions or otherwise signal the access control logic 210 and/or control module 202 of a respective cache memory element 110, 112, 114, 116, 118 for an initial (or default) write duty cycle and an initial (or default) read duty cycle…”);
provide first and second column select signals to the column selection circuitry responsive to a second control signal (SCHREIBER teaches read-cycle column select signals and write-cycle column select signals generated from control input, figures 2 and 3, “second control signal” has been interpreted as read duty cycle/write duty cycle control signal, the duty-cycle configuration signal controlling pulse generator 212 constitutes a control signal because it determines the operation mode of the memory (read cycle or write cycle)), and where the first column select signal is to control a read operation (SCHREIBER teaches, during a read cycle, use column select signal to couple bitline to read circuitry 208, [0022], “…access control logic 210 concurrently asserts or otherwise provides a column select signal to the column select circuitry of the SRAM array 204 to couple the bit line(s) associated with the addressed SRAM cell to the appropriate access circuitry 206, 208, thereby enabling access to the addressed SRAM cell…”, [0030], “…the access control logic 210 and/or word line decode logic 214 assert or otherwise provide appropriate word line select and column select signals to enable reading data from addressed SRAM cells in the SRAM array 204 back to the memory controller 108 via the read circuitry 208…”) and the second column select signal is to control a write operation (SCHREIBER teaches, during a write cycle, use column select signal to couple bitline to write circuitry 206, [0029], “…the appropriate word line select signal is asserted for that duration, the SRAM cells of that row of the SRAM array 204 are coupled to their corresponding bit line(s) that are configured to receive the data to be written from write circuitry 206 via column select circuitry. The column select signals provided by the access control logic 210 operate the column select circuitry to couple bit line(s) of the addressed SRAM cell to the output of the write circuitry 206 to write data to the addressed SRAM cell while the word line select signal is asserted…”).
and a transition of the second control signal defines completion of the read operation and simultaneously defines initiation of the write operation (Schreider teaches that access control logic configures pulse generator 212 to generate pulses corresponding to read duty cycles or write duty cycles depending on the operational mode of the memory ([0023]-[0025]). When the control logic transitions the configuration of the oulse generator from the read cycle to the write cycle, the memory operation correspondingly transitions from a read operation to a write operation. Accordingly, the transition of the duty-cycle control configuration defines completion of the read operation and initiation of the write operation).
Regarding claim 2, SCHREIBER teaches the storage device of claim 1, where the control circuitry is to, in a second mode of operation (in a different read/write duty cycle configurations, SCHREIBER teaches where different WL pulses and column select sequences are used): provide a second wordline select signal (in a different read/write duty cycle configurations, SCHREIBER teaches asserting a WL select signal via pulse generator 212 under control of access control logic 210, [0021]-[0023]) to the wordline selection circuitry responsive to the first control signal; provide third (SCHREIBER teaches, during a read cycle, use column select signal to couple bitline to read circuitry 208) and fourth column select signals (SCHREIBER teaches, during a write cycle, use column select signal to couple bitline to write circuitry 206) to the column selection circuitry responsive to the first control signal, and where the third column select signal (SCHREIBER teaches, during a read cycle, use column select signal to couple bitline to read circuitry 208) is to control a read operation and where the fourth column select signal (SCHREIBER teaches, during a write cycle, use column select signal to couple bitline to write circuitry 206) is to control a write operation.
Regarding claim 3, SCHREIBER teaches the storage device of claim 1, where the first control signal comprises a first global timing signal comprising two or more pulses (SCHREIBER teaches that first control signal (read or write instruction input) causes the pulse generator 212 to generate multiple timing pulses for activating the wordline).
Regarding claim 4, SCHREIBER teaches the storage device of claim 1, where the second control signal (“second control signal” has been interpreted as read duty cycle/write duty cycle control signal) is generated responsive to the first control signal (SCHREIBER teaches that internal read/write duty-cycle control is generated responsive to the external read/write instruction, [0027]/[0030]).
Regarding claim 5, SCHREIBER teaches the storage device of claim 4, where the second control signal is generated responsive to a third control signal being asserted (SCHREIBER teaches that additional signal, e.g., test interface 130, mode-selection inputs, modify the duty-cycle control, [0030]).
Regarding claim 6, SCHREIBER teaches the storage device of claim 4, where the first control signal (“first control signal” has been interpreted as read or write instructions in [0027]) is received at a first input of the control circuitry and where the third control signal (“third control signal” has been interpreted as interface 130 or configuration control in [0027]/[0029]) is received at a second input of the control circuitry.
Regarding claim 8, SCHREIBER teaches the storage device of claim 7, where the write operation is to start after a pre-defined delay following the first column select signal (SCHREIBER teaches read-cycle duration and write-cycle duration separated by defined timing intervals controlled by pulse generator 212, [0030]-[0035] describes timing separation between read cycle and write cycle pulses).
Regarding claim 9, SCHREIBER teaches the storage device of claim 1, where the column selection circuitry comprises one or more column read devices and where the first column select signal is to enable a first column read device to couple a bitline to sense amplifier circuitry (SCHREIBER teaches in figure 2 and [0022], [0023] that read circuitry 208 connected to bitlines via column select logic 210).
Regarding claim 10, SCHREIBER teaches the storage device of claim 1, where the column selection circuitry comprises one or more column write devices and where the second column select signal is to enable a first column write device to couple a bitline to write driver circuitry (SCHREIBER teaches in figure 2 and [0022], [0024] that write circuitry 206 connected to bitlines via column select logic 210).
Regarding claim 13, SCHREIBER teaches the storage device of claim 1, where the first control signal comprises two clock pulses and where the third control signal comprises a single pulse having a length substantially similar to the total length of the two clock pulses of the first control signal (SCHREIBER teaches in [0027]/[0030] that pulse generator 212 produces multi-ulseWL timing sequences and single-pulse sequences depending on duty cycle configurations).
Regarding claim 14, SCHREIBER teaches the storage device of claim 1, where the read and write operation comprises an eviction and allocation operation (Eviction/allocation can be performed by software/controller on any read/write memory, thus if a memory performs a read (to fetch victim data) and then a write (to overwrite it), that sequence is an eviction and allocation operation, SCHREIBER teaches a cache memory system controlled by memory controller 108 which performs read and write operations to cache memory elements. Such controller-directed replacement inherently includes eviction of stored data and allocation of new data).
Regarding independent claim 15, SCHREIBER teaches a method of controlling a read operation and a write operation at a storage device, the storage device (figure 2) having:
core circuitry comprising one or more bitcells (204 in figure 2, [0021], “…the SRAM array 204…”), each bitcell accessible via a corresponding bitline (“bit lines indicated in [0021], “…SRAM array 204 includes column select circuitry configured to select or otherwise enable access to (e.g., writing to and/or reading from) a particular column of cells within the SRAM array 204 by coupling the bit line(s) of a selected column to the access circuitry 206, 208 in response to signals from the control module 202…”) and wordline (“word line” indicated in [0021], “…the control module 202 asserts a word line select signal for a particular row of the SRAM array 204 that includes an addressed SRAM cell (e.g., the SRAM cell to be accessed)…”);
column selection circuitry (“column select circuitry” in [0022]) to, responsive to a column select signal (“column select signal” in [0022], “…access control logic 210 concurrently asserts or otherwise provides a column select signal to the column select circuitry of the SRAM array 204 to couple the bit line(s) associated with the addressed SRAM cell to the appropriate access circuitry 206, 208, thereby enabling access to the addressed SRAM cell…”), select at least one bitcell via one or more bitlines;
wordline selection circuitry to, responsive to a wordline select signal (“wordline select signal” in [0020], “…the control module 202 asserts a word line select signal for a particular row of the SRAM array 204 that includes an addressed SRAM cell (e.g., the SRAM cell to be accessed)…”), select the at least one bitcell via one or more wordlines;
control circuitry (202 in figure 2) to, in a first mode of operation (SCHREIBER teaches various read/write duty cycle configurations), the method comprising: providing, from the control circuitry operating in the first mode to the wordline selection circuitry, a first wordline select signal responsive to a first control signal (SCHREIBER teaches asserting a WL select signal via pulse generator 212 under control of access control logic 210, [0021]-[0023], “first control signal” has been interpreted as read or write instructions in [0027], “..memory controller 108 may provides instructions or otherwise signal the access control logic 210 and/or control module 202 of a respective cache memory element 110, 112, 114, 116, 118 for an initial (or default) write duty cycle and an initial (or default) read duty cycle…”);
providing, from the control circuitry operating in the first mode to the column selection circuitry, first and second column select signals responsive to a second control signal (SCHREIBER teaches read-cycle column select signals and write-cycle column select signals generated from control input, figures 2 and 3, “second control signal” has been interpreted as read duty cycle/write duty cycle control signal), and where the first column select signal is to control a read operation (SCHREIBER teaches, during a read cycle, use column select signal to couple bitline to read circuitry 208, [0022], “…access control logic 210 concurrently asserts or otherwise provides a column select signal to the column select circuitry of the SRAM array 204 to couple the bit line(s) associated with the addressed SRAM cell to the appropriate access circuitry 206, 208, thereby enabling access to the addressed SRAM cell…”, [0030], “…the access control logic 210 and/or word line decode logic 214 assert or otherwise provide appropriate word line select and column select signals to enable reading data from addressed SRAM cells in the SRAM array 204 back to the memory controller 108 via the read circuitry 208…”) and the second column select signal is to control a write operation (SCHREIBER teaches, during a write cycle, use column select signal to couple bitline to write circuitry 206, [0029], “…the appropriate word line select signal is asserted for that duration, the SRAM cells of that row of the SRAM array 204 are coupled to their corresponding bit line(s) that are configured to receive the data to be written from write circuitry 206 via column select circuitry. The column select signals provided by the access control logic 210 operate the column select circuitry to couple bit line(s) of the addressed SRAM cell to the output of the write circuitry 206 to write data to the addressed SRAM cell while the word line select signal is asserted…”).
And a transition of the second control signal defines completion of the read operation and simultaneously defines initiation of the write operation (Schreider teaches that access control logic configures pulse generator 212 to generate pulses corresponding to read duty cycles or write duty cycles depending on the operational mode of the memory ([0023]-[0025]). When the control logic transitions the configuration of the pulse generator from the read cycle to the write cycle, the memory operation correspondingly transitions from a read operation to a write operation. Accordingly, the transition of the duty-cycle control configuration defines completion of the read operation and initiation of the write operation).
Regarding claim 16, SCHREIBER teaches the method of claim 15, further comprising: providing, from the control circuitry operating in the second mode (in a different read/write duty cycle configurations, SCHREIBER teaches where different WL pulses and column select sequences are used) to the wordline selection circuitry, a second wordline select signal (in a different read/write duty cycle configurations, SCHREIBER teaches asserting a WL select signal via pulse generator 212 under control of access control logic 210, [0021]-[0023]) responsive to the first control signal; providing, from the control circuitry operating in the second mode to the column selection circuitry, third (SCHREIBER teaches, during a read cycle, use column select signal to couple bitline to read circuitry 208) and fourth column select signals (SCHREIBER teaches, during a write cycle, use column select signal to couple bitline to write circuitry 206) responsive to the first control signal, and where the third column select signal is to control a read operation and where the fourth column select signal (SCHREIBER teaches, during a write cycle, use column select signal to couple bitline to write circuitry 206) is to control a write operation.
Regarding claim 17, SCHREIBER teaches a non-transitory computer-readable medium to store computer-readable code for fabrication of the storage device of claim 1 (SCHREIBER teaches in [0027], [0030] the logic structure and operational control of the device).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over SCHREIBER PG PUB 20120147682 (hereinafter SCHREIBER), in view of Song US Patent 7359266 (hereinafter Song).
Regarding claim 11, SCHREIBER teaches the storage device of claim 1, but does not teach the storage device further comprising precharge circuitry to precharge a bitline.
However, Song teaches in figure 2 a precharge circuit connected to the complementary bit lines.
Precharge circuit is widely used in SRAM arrays to store bitline levels before access. It would have been obvious to one of the ordinary skill to incorporate the well-known precharge circuit of Song to SRAM memory device of SCHREIBER such that the storage device further comprising precharge circuitry to precharge a bitline, in order to have a working device.
Regarding claim 12, the combination of SCHREIBER and Song teaches the storage device of claim 11, where the precharge circuitry is not activated between a read operation and a write operation in the first mode of operation (Song teaches precharge actions can be disabled, suppressed, or weakened depending on the cycle timing ad operation mode, e.g., inactive weak precharging mode for high-speed operation, or precharge enable signals that may be withheld during specific transitions. It would have been obvious to one of the ordinary skill to realize duty-cycle timing separation of SCHREIBER and timing-controlled precharge suppression of Song such that to disable precharge between a read and immediately following write to reduce latency and improve timing performance).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XIAOCHUN L CHEN whose telephone number is (571)272-0941. The examiner can normally be reached M-F: 9AM-5:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at 571-272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/XIAOCHUN L CHEN/Primary Examiner, Art Unit 2824