Prosecution Insights
Last updated: August 16, 2026
Application No. 18/779,831

CAPACITOR DEVICE AND SEMICONDUCTOR DEVICE

Non-Final OA §102§103
Filed
Jul 22, 2024
Priority
Jan 27, 2022 — JP 2022-011036 +1 more
Examiner
AHMAD, KHAJA
Art Unit
Tech Center
Assignee
Rohm Co., Ltd.
OA Round
1 (Non-Final)
81%
Grant Probability
Favorable
1-2
OA Rounds
3m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
766 granted / 946 resolved
+21.0% vs TC avg
Strong +26% interview lift
Without
With
+26.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
38 currently pending
Career history
992
Total Applications
across all art units

Statute-Specific Performance

§101
1.5%
-38.5% vs TC avg
§103
59.5%
+19.5% vs TC avg
§102
27.6%
-12.4% vs TC avg
§112
5.5%
-34.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 946 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION This office action is in response to the application filed on 07/22/2024. Currently, claims 1-20 are pending in the application. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-10 and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al (US 20140116761 A1). Regarding claim 1, Figures 1-5 of Lee disclose a capacitor device comprising: a capacitor element (50, [0082]); an insulating cover (60) covering the capacitor element; a first external electrode (180) exposed from the insulating cover; a second external electrode (181) exposed from the insulating cover; a first conductive member (170) electrically conducting to the first external electrode and the capacitor element; and a second conductive member (171) electrically conducting to the second external electrode and the capacitor element, wherein the capacitor element includes a multilayer body comprising a plurality of dielectric layers (30) and a plurality of conductor layers (1/2) alternately laminated in a first direction, the insulating cover (60) covers an entirety of the capacitor element except a connection portion where the capacitor element and the first conductive member are connected and a connection portion where the capacitor element and the second conductive member are connected, and the first external electrode (180) and the second external electrode (181) are formed on opposite sides of each other in the first direction (vertical in the Figure). Regarding claim 2, Figures 1-5 of Lee disclose that the capacitor device according to claim 1, wherein the capacitor element (50) includes a first aggregate electrode (110) to which the first conductive member (170, [0085]) is connected and a second aggregate electrode (120) to which the second conductive member (171, [0085]) is connected, and the plurality of conductor layers (1) include a plurality of first electrode layers connected to the first aggregate electrode and a plurality of second electrode layers (2) connected to the second aggregate electrode. Regarding claim 3, Figures 1-5 of Lee disclose that the capacitor device according to claim 2, wherein the multilayer body includes an obverse surface (150) and a reverse surface (130) spaced apart in the first direction, the insulating cover (160) includes an obverse covering portion covering the obverse surface and a reverse covering portion covering the reverse surface, the first external electrode (180) covers a part of the obverse covering portion, and the second external electrode (181) covers a part of the reverse covering portion. Regarding claim 4, Figures 1-5 of Lee disclose that the capacitor device according to claim 3, wherein the multilayer body includes a first side surface (left side surface of 50) and a second side surface (right side surface of 50) spaced apart in a second direction orthogonal to the first direction, each of the first side surface and the second side surface is connected to the obverse surface (150) and the reverse surface (130), the first aggregate electrode (110) includes a first side electrode portion covering the first side surface, and the second aggregate electrode (120) includes a second side electrode portion covering the second side surface. Regarding claim 5, Figures 1-5 of Lee disclose that the capacitor device according to claim 4, wherein the first aggregate electrode (110) includes a first obverse electrode portion covering a part of the obverse surface and a first reverse electrode portion covering a part of the reverse surface, the first obverse electrode portion and the first reverse electrode portion are connected to the first side electrode portion, the second aggregate electrode (120) includes a second obverse electrode portion covering a part of the reverse surface and a second reverse electrode portion covering a part of the reverse surface, and the second obverse electrode portion and the second reverse electrode portion are connected to the second side electrode portion. Regarding claim 6, Figures 1-5 of Lee disclose that the capacitor device according to claim 5, wherein the first conductive member (170) penetrates the insulating cover (60) in the first direction (vertical direction in the Figure 5), and the second conductive member (171) penetrates the insulating cover in the first direction. Regarding claim 7, Figures 1-5 of Lee disclose that the capacitor device according to claim 6, wherein the first conductive member (170) is in contact with the first obverse electrode portion (of 110 at 150), and the second conductive member (171) is in contact with the second reverse electrode portion (of 120 at 130). Regarding claim 8, Figures 1-5 of Lee disclose that the capacitor device according to claim 6, wherein the first conductive member (170) is in contact with the first side electrode portion, and the second conductive member (171) is in contact with the second side electrode portion. Regarding claim 9, Figures 1-5 of Lee disclose that the capacitor device according to claim 3, further comprising: one or more first vias (at 170) that penetrate the obverse covering portion in the first direction and are in contact with the obverse surface; and one or more second vias (at 171) that penetrate the reverse covering portion in the first direction and are in contact with the reverse surface. Regarding claim 10, Figures 1-5 of Lee disclose that the capacitor device according to claim 9, wherein the one or more first vias (at 170) are connected to the first external electrode (180), and the one or more second vias (at 171) are connected to the second external electrode (181). Regarding claim 16, Figures 1-5 of Lee disclose that the capacitor device according to claim 1, wherein at least one of the plurality of conductor layers, the first external electrode or the second external electrode includes a neck pattern portion where a conduction path is partially narrowed (180 and 181 has narrow area going to 110 and 120). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 11-13 are rejected under 35 U.S.C. 103 as being obvious over Lee et al (US 20140116761 A1) in view of TANAKA (WO 2016170894 A1). An English machine translation of TANAKA is attached with office action. Regarding claims 11-13, Figures 1-5 of Lee do not teach that the capacitor device according to claim 1, wherein the capacitor element is a first capacitor element, and the capacitor device further comprises a second capacitor element, wherein the first capacitor element and the second capacitor element are electrically connected in parallel or wherein the first capacitor element and the second capacitor element are electrically connected in series. However, TANAKA is a pertinent art which teaches a laminated chip capacitor wherein a main body includes a first electrode layer, a second electrode layer, and a dielectric layer that is disposed between the first electrode layer and the second electrode layer. Figures 8A-8B of TANAKA teaches such capacitor to be connected in series or parallel for achieving a specific capacitance for stable power (Page 6 of English translation of TANAKA). Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the capacitor device of Lee as claimed above according to the teaching of TANAKA in order to form small or larger capacitance for stable power. Claims 14-15 are rejected under 35 U.S.C. 103 as being obvious over Lee et al (US 20140116761 A1). Regarding claims 14-15, Figures 1-5 of Lee do not teach that the capacitor device according to claim 1, wherein a constituent material of the insulating cover and a constituent material of the dielectric layers are different. Or The capacitor device according to claim 1, wherein the first external electrode and the second external electrode include a Ni—P layer. However, the Examiner takes an official notice that such limitations are well known in pertinent prior arts. Claims 17-20 are rejected under 35 U.S.C. 103 as being obvious over Lee et al (US 20140116761 A1) in view of OTAKE (US 20170229953 A1). Regarding claims 17-20, Figures 1-5 of Lee do not teach that the semiconductor device comprising: the capacitor device as set forth in claim 1; and a first switching element and a second switching element connected in series to form a bridge, wherein the first external electrode and the second external electrode are electrically connected to opposite ends of the bridge and further comprising: a first mount portion on which the first switching element is mounted; and a second mount portion on which the second switching element is mounted, wherein the first mount portion and the second mount portion are spaced apart from each other, and the first mount portion faces at least a part of the capacitor device in the first direction. Or wherein the first switching element and the second switching element comprises SiC. Or further comprising a passive element electrically connected in series to the capacitor device. However, OTAKE is a pertinent art which teaches a power module includes: a bridge unit including a bridge circuit composed including a plurality of SiC-MOSFETs Q1 and Q2 and an internal capacitor C1/C2 connected so as to extend over between both ends of the bridge circuit; power terminals P and N of which one ends are respectively connected to both ends of the bridge unit and other ends are respectively exposed to the outside; and a snubber circuit (RB, CB) connected so as to extend over between an exposed side of the positive-side power terminal P and an exposed side of the negative-side power terminal N. A power circuit comprising the power module, and a smoothing capacitor C1/C2 connected in parallel to the snubber circuit. There can be provided the power module and the power circuit which can simultaneously realize the low parasitic inductance and the low noise. Figure 1 of OTAKE teaches such power module with a bridge 3 comprising a first switching element and a second switching element connected in series to form the bridge and wherein the first external electrode and the second external electrode of capacitor C1/C2 are electrically connected to opposite ends of the bridge and wherein the first switching element and the second switching element comprises SiC ([0039]). Figures 19-20 of OTAKE, further, teaches that the transistor Q1 and Q2 are spaced apart and mounted separately in the module and a passive element (L) electrically connected in series to the capacitor device C2. Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the capacitor device of Lee as claimed above according to the teaching of OTAKE in order to make a power module with low parasitic inductance and the low noise (Abstract of OTAKE). Examiner Notes A reference to specific paragraphs, columns, pages, or figures in a cited prior art reference is not limited to preferred embodiments or any specific examples. It is well settled that a prior art reference, in its entirety, must be considered for all that it expressly teaches and fairly suggests to one having ordinary skill in the art. Stated differently, a prior art disclosure reading on a limitation of Applicant's claim cannot be ignored on the ground that other embodiments disclosed were instead cited. Therefore, the Examiner's citation to a specific portion of a single prior art reference is not intended to exclusively dictate, but rather, to demonstrate an exemplary disclosure commensurate with the specific limitations being addressed. In re Heck, 699 F.2d 1331, 1332-33,216 USPQ 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (CCPA 1968)). In re: Upsher-Smith Labs. v. Pamlab, LLC, 412 F.3d 1319, 1323, 75 USPQ2d 1213, 1215 (Fed. Cir. 2005); In re Fritch, 972 F.2d 1260, 1264, 23 USPQ2d 1780, 1782 (Fed. Cir. 1992); Merck& Co. v. BiocraftLabs., Inc., 874 F.2d 804, 807, 10 USPQ2d 1843, 1846 (Fed. Cir. 1989); In re Fracalossi, 681 F.2d 792,794 n.1, 215 USPQ 569, 570 n.1 (CCPA 1982); In re Lamberti, 545 F.2d 747, 750, 192 USPQ 278, 280 (CCPA 1976); In re Bozek, 416 F.2d 1385, 1390, 163 USPQ 545, 549 (CCPA 1969). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAJA AHMAD whose telephone number is (571)270-7991. The examiner can normally be reached on Monday-Friday, 8:00 AM - 5:00 PM (Eastern Time). If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GAUTHIER STEVEN B, can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice . Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KHAJA AHMAD/Primary Examiner, Art Unit 2813
Read full office action

Prosecution Timeline

Jul 22, 2024
Application Filed
Jul 21, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
81%
Grant Probability
99%
With Interview (+26.0%)
2y 4m (~3m remaining)
Median Time to Grant
Low
PTA Risk
Based on 946 resolved cases by this examiner. Grant probability derived from career allowance rate.

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