Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, 14-18, and 21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al, US 20210249491.
Regarding claim 1, Kim discloses : A display device, comprising: a first thin film transistor, a second thin film transistor, and a third thin film transistor(Fig. 5; #T7, #T6, and #T1), each of the first thin film transistor, the second thin film transistor, and the third thin film transistor including: a semiconductor layer, a gate electrode on the semiconductor layer, and a first electrode and a second electrode adjacent to the gate electrode(#173, #sd71, and #sd72 for #T7; #172, #sd61, and #sd62 for t6; and #141, #sd11, and #sd12 for #T1); a first connection line between the first thin film transistor and the second thin film transistor(#T6 connected to #T7); and a second connection line between the second thin film transistor and the third thin film transistor(#T6 connected through #LK3 and #CNT9), wherein connection between the semiconductor layer of the first thin film transistor and the semiconductor layer of the second thin film transistor via the first connection line differs from connection between the semiconductor layer of the second thin film transistor and the semiconductor layer of the third thin film transistor via the second connection line(conductive elements connecting #T7 and #T6 are in layers #via and #PDL and conductive elements connecting #T6 and #T1 are in #idl4).
Regarding claim 2, Kim discloses : The display device of claim 1, wherein the semiconductor layer of the first thin film transistor, the semiconductor layer of the second thin film transistor, and the semiconductor layer of the third thin film transistor each include an oxide(transistors semiconductor layers may include an oxide [0115, 0142, 0170].
Regarding claim 14, Kim discloses : The display device of claim 1, wherein an emission control signal is applied to the gate electrode of the second thin film transistor(Fig. 3, #EM connected to #T6), the first electrode of the second thin film transistor is electrically connected to the second electrode of the first thin film transistor(#T6 connected to #T7), and the second electrode of the second thin film transistor is electrically connected to the second electrode of the third thin film transistor(#T6 connected to #T1).
Regarding claim 15, Kim discloses : The display device of claim 14, wherein the second thin film transistor is an emission control transistor(#T6 is an emission control transistor [0072]).
Regarding claim 16, Kim discloses : The display device of claim 1, further comprising a capacitor disposed between the second electrode of the first thin film transistor and the third thin film transistor(Fig. 5, #cst disposed in layer between #T7 and #T1).
Regarding claim 17, Kim discloses : The display device of claim 16, wherein the gate electrode of the third thin film transistor is electrically connected to the capacitor(Fig. 4, #T1 connected to #cst), a high potential voltage is applied to the first electrode of the third thin film transistor(#ELVDD connected to #T1 [0075]), and the second electrode of the third thin film transistor is electrically connected to the second electrode of the second thin film transistor(#T1 connected to #T6).
Regarding claim 18, Kim discloses : The display device of claim 17, wherein the third thin film transistor is a driving transistor(#T1 is a driving transistor [0071]).
Regarding claim 21, Kim discloses : A display device, comprising: a substrate; a first thin film transistor and a second thin film transistor adjacent to the first thin film transistor on the substrate(Fig. 5, #T6 and #T7); a connection line between the first thin film transistor and the second thin film transistor(#T6 connected to #T7 through #ANO), the connection line electrically connecting the first thin film transistor and the second thin film transistor(#T6 connected to #T7 through #ANO; a light emitting element electrically connected to at least one of the first thin film transistor and the second thin film transistor(#ANO connected to #EL); wherein the first thin film transistor and the second thin film transistor each includes: a semiconductor layer on a first layer(#Fig. 19, #ACT6 and #ACT7 on #FS3), a gate electrode on a second layer(#Fig. 20, #172 and #173 on top of layer #GI3), and a first electrode and a second electrode adjacent to the gate electrode(Fig.5, #162 and #182 adjacent to #172, #163 and #183 adjacent to #173)) , the first electrode and the second electrode on a third layer(#182 on top of #SD62 and #183 on top of layer #sd72), wherein the connection line electrically connecting the first thin film transistor and the second thin film transistor is on a different layer from the first, second, and third layers(#ANO on #PDL).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al, US 20210249491.
Regarding claim 3, Kim discloses : The display device of claim 1.
Kim does not disclose : wherein the semiconductor layer of the first thin film transistor and the semiconductor layer of the second thin film transistor are electrically connected through the first connection line located coplanarly with the semiconductor layer.
However, Kim teaches : wherein the semiconductor layer of the first thin film transistor and the semiconductor layer of the second thin film transistor are electrically connected through the first connection line located coplanarly with the semiconductor layer(Coplanar transistors #T1 and #T3 include a coplanar conductive element #LK1 that is formed in the same layer coplanar to #ACT1 and #ACT2).
It would have been obvious to one of ordinary skill in the art at the time of the invention to apply the teachings of conductive element #LK1 between #T1 and #T3 to #T6 and #T7 because the known technique of forming a conductive element between transistor on the same layer for the predictable result of electrical connection was recognized as part of ordinary capabilities of one skilled in the art. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 4, Kim teaches : The display device of claim 3.
Kim teaches : wherein the semiconductor layer and the first connection line include a same material(Fig. 13, #LK1 from the same layer as #ACT1 [0139, 0199].
Regarding claim 5, Kim teaches : The display device of claim 3.
Kim teaches : wherein a first scan signal is applied to the gate electrode of the first thin film transistor(Scan signal applied to #T7 [0085]), an initialization voltage is applied to the first electrode of the first thin film transistor(#T7 may be electrically connected to initialization voltage), and the second electrode of the first thin film transistor is electrically connected to the first electrode of the second thin film transistor(Fig. 4, #T7 connected to #T6).
Regarding claim 6, Kim teaches : The display device of claim 5.
Kim teaches : wherein the first thin film transistor is an initialization transistor(Fig. 4, #T7 connected to #VINT [0085]).
Regarding claim 7, Kim teaches : The display device of claim 3.
Kim teaches : wherein an emission control signal is applied to the gate electrode of the second thin film transistor(Fig. 4, #EM applied to #T6), the first electrode of the second thin film transistor is electrically connected to the second electrode of the first thin film transistor(#T6 connected to #T7), and the second electrode of the second thin film transistor is electrically connected to the second electrode of the third thin film transistor(#T6 connected to #T1).
Regarding claim 8, Kim teaches : The display device of claim 7.
Kim teaches : wherein the second thin film transistor is an emission control transistor(#T6 is an emission control transistor [0083]).
Claim(s) 9-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al, US 20210249491 in view of Yun, US 20220208932.
Regarding claim 9, Kim discloses : The display device of claim 1.
Kim does not disclose : wherein the semiconductor layer of the second thin film transistor and the semiconductor layer of the third thin film transistor are electrically connected through the second connection line located at a different layer from the semiconductor layer.
However, in the same field of endeavor, Yun teaches : wherein the semiconductor layer of the second thin film transistor and the semiconductor layer of the third thin film transistor are electrically connected through the second connection line located at a different layer from the semiconductor layer(Fig. 5, #BML bottom metal layer disposed below and electrically connecting the driving and initialization transistor(0010]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Yun to Kim to include a connection line in a different layer from the semiconductor layer to simplify a multilayer display structure (Yun [0210]).
Regarding claim 10, Kim as modified by Yun discloses : The display device of claim 9.
Yun teaches : wherein the second connection line is disposed under the semiconductor layer(Fig. 5, #BML disposed below a driving transistor and initialization transistor [0010]).
Regarding claim 11, Kim as modified by Yun discloses : The display device of claim 9.
Kim teaches : wherein the semiconductor layer of the second thin film transistor and the first connection line are electrically connected through the second electrode of the second thin film transistor(Fig. 4 and fig. 5; #T6 connected to #T7) , and the semiconductor layer of the third thin film transistor and the second connection line are electrically connected to the second electrode of the third thin film transistor(#T1 connected to #T6).
Regarding claim 12, Kim as modified by Yun discloses : The display device of claim 1.
Kim teaches : wherein a first scan signal is applied to the gate electrode of the first thin film transistor(Fig. 4; #GB applied to #T7), an initialization voltage is applied to the first electrode of the first thin film transistor(#VINT applied to #T7), and the second electrode of the first thin film transistor is electrically connected to the first electrode of the second thin film transistor(Fig. 4 and fig. 5; #T7 connected to #T6).
Regarding claim 13, Kim as modified by Yun discloses : The display device of claim 12.
Kim teaches : wherein the first thin film transistor is an initialization transistor(#T7 is an initialization transistor [0072]).
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al, US 20210249491 in view of Sonoda et al, US 20220190291
Regarding claim 19, Kim discloses : A display device, comprising: a substrate; a first thin film transistor, a second thin film transistor, and a third thin film transistor on the substrate, the first thin film transistor, the second thin film transistor, and the third thin film transistor each including(Fig. 5, #T1, #T3, and #T4): a semiconductor layer, a gate electrode on the semiconductor layer, and a first electrode and a second electrode adjacent to the gate electrode(Transistors may include a gate electrode, source drain electrodes, and semiconductor patterns [0071, 0094]; a first connection line(#LK1 made of semiconductor material [0140]), the semiconductor layer of the first thin film transistor and the semiconductor layer of the second thin film transistor being electrically connected through the first connection line(#LK1 connecting #T1 and #T3); and a second connection line, the semiconductor layer of the second thin film transistor and the semiconductor layer of the third thin film transistor being electrically connected through the second connection line(#t3 and #t4 connected through conductive features #132 and #123 where #132 and #123 are made of metal [0126, 0135]).
Kim does not disclose : wherein a reflectance of the first connection line is lower than a reflectance of the second connection line.
However, in the same field of endeavor, Sonoda teaches : wherein a reflectance of the first connection line is lower than a reflectance of the second connection line(metal layers have a higher reflectance than semiconductor layer [0091]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Sonoda to Kim since an oxide semiconductor material inherently has a lower reflectance than metal (Sonada [0091]).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al, US 20210249491 in view of Sonoda et al, US 20220190291, in further view of Liu et al, US 12701860.
Regarding claim 20, Kim as modified by Sonoda discloses : The display device of claim 19.
Kim teaches : wherein the first connection line is located coplanarly with the semiconductor layer(Fig. 5, #LK1 formed same layer as #ACT1 and #ACT3).
Kim as modified by Sonoda does not disclose : the second connection line is located under the semiconductor layer.
However, in the same field of endeavor, Liu teaches : the second connection line is located under the semiconductor layer(Fig. 3, #52 located below and connecting #T4 and #T2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Liu to Kim and Sonoda to improve a pixel per inch of a display device (Liu; Col. 15, line 30-41).
Claim(s) 22-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al, US 20210249491 in view of Liu et al, US 12701860.
Regarding claim 22, Kim discloses : The display device of claim 21.
Kim does not disclose : further comprising: a light blocking layer overlapping the semiconductor layer of either the first thin film transistor or the second thin film transistor, wherein the connection line is on a same layer as the light blocking layer.
However, in the same field of endeavor, Liu teaches : further comprising: a light blocking layer overlapping the semiconductor layer of either the first thin film transistor or the second thin film transistor(Fig. 3, #54), wherein the connection line is on a same layer as the light blocking layer(#54 in same layer as #52).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Liu to Kim to provide a light blocking layer overlapping the semiconductor layer of a transistor to ensure a transistor is not affected by light (Liu [Col. 11, line 53-62]).
Regarding claim 23, Kim as modified by Liu discloses : The display device of claim 22.
Liu teaches : wherein the connection line is spaced apart from the light blocking layer from a plan view(Fig. 3, #54 on same layer as #52 and not overlapping), wherein the light blocking layer and the connection line are made of a same material(#32 includes #54 and #52 [Col. 11, line 53-62]).
Regarding claim 24, Kim as modified by Liu discloses : The display device of claim 22.
Liu teaches : wherein the connection line electrically connects the first electrode of the first thin film transistor and the first electrode of the second thin film transistor(Fig. 3, #52 overlapping #t42 and #t22), wherein the connection line overlaps with the first electrode of the first thin film transistor and the first electrode of the second thin film transistor from a plan view, and wherein the connection line does not overlap with the second electrode of the first thin film transistor and the second electrode of the second thin film transistor from a plan view(#52 not overlapping #t41 and #t21).
Claim(s) 25 and 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al, US 20210249491 in view of Cho et al, US 20210249498.
Regarding claim 25, Kim discloses : The display device of claim 21.
Kim does not disclose : further comprising: a light blocking layer overlapping the semiconductor layer of either the first thin film transistor or the second thin film transistor, wherein the connection line is on a different layer as the light blocking layer.
However, in the same field of endeavor, Cho teaches : a light blocking layer overlapping the semiconductor layer of either the first thin film transistor or the second thin film transistor(Fig. 4, #183 overlapping #T4 [0152]), wherein the connection line is on a different layer as the light blocking layer(#183 on a different layer than #171).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a connection line on a different layer than the light blocking layer, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Regarding claim 26, Kim as modified by Cho discloses : The display device of claim 25.
Cho teaches : wherein the connection line is closer to the substrate than the light blocking layer(#171 closer to substrate than #183).
Claim(s) 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al, US 20210249491 in view of Cho et al, US 20210249498 in further view of Nam et al, US 20230189585.
Regarding claim 27, Kim as modified by Cho discloses : The display device of claim 25.
Kim as modified by Cho does not disclose : wherein the light blocking layer is closer to the substrate than the connection line.
However, in the same field of endeavor, Nam teaches : wherein the light blocking layer is closer to the substrate than the connection line(Fig. 5, #tft1 connected to #tft2 through #bre2 and #slp under #act1 with #slp being closer to the substrate than #bre2).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a light blocking layer closer to the substrate, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Claim(s) 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al, US 20210249491 in view of Cho et al, US 20210249498 in further view of Cho et al, US 20230263011, hereafter ‘011.
Regarding claim 28, Kim as modified by Cho discloses : The display device of claim 25.
Kim as modified by Cho does not disclose : wherein the connection line is spaced apart from the light blocking layer from a plan view, wherein the light blocking layer and the connection line are made of a different material.
However, in the same field of endeavor, ‘011 teaches : wherein the connection line is spaced apart from the light blocking layer from a plan view(Fig. 8, #twl does not overlap #BMLa), wherein the light blocking layer and the connection line are made of a different material(#twl and light blocking structure are different materials [0127]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of ‘011 to Kim and Cho to have connections line and light blocking structures made of different materials.
Claim(s) 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al, US 20210249491 in view of Cho et al, US 20210249498.
Regarding claim 29, Kim as modified by Cho discloses : The display device of claim 25.
Kim as modified by Cho does not disclose : wherein the connection line electrically connects the first electrode of the first thin film transistor and the first electrode of the second thin film transistor, wherein the connection line overlaps with the first electrode of the first thin film transistor and the first electrode of the second thin film transistor from a plan view, and wherein the connection line does not overlap with the second electrode of the first thin film transistor and the second electrode of the second thin film transistor from a plan view.
However, in the same field of endeavor, Liu teaches : wherein the connection line electrically connects the first electrode of the first thin film transistor and the first electrode of the second thin film transistor(Fig. 3, #t4 connected to #t2 through #52), wherein the connection line overlaps with the first electrode of the first thin film transistor and the first electrode of the second thin film transistor from a plan view(#52 overlaps #t42 and #t22), and wherein the connection line does not overlap with the second electrode of the first thin film transistor and the second electrode of the second thin film transistor from a plan view(#52 does not overlap #t41 and #t21).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to configure the connection line to overlap particular electrodes, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Claim(s) 30-32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al, US 20210249491 in view of Cha et al, US 20220406877.
Regarding claim 30, Kim discloses : A display device, comprising: a substrate(Fig. 5, #sub); a first thin film transistor and a second thin film transistor adjacent to the first thin film transistor on the substrate(#T3 connected to #T6); a connection line on the substrate and between the first thin film transistor and the second thin film transistor from a plan view, the connection line electrically connecting the first thin film transistor and the second thin film transistor(#T3 connected to #T6 through #162 and #LK1), a light emitting element electrically connected to at least one of the first thin film transistor and the second thin film transistor(#T6 connected to #EL); wherein the first thin film transistor and the second thin film transistor each includes: a semiconductor layer on the substrate(#ACT3 and #ACT6), a gate electrode adjacent to the semiconductor layer(#142 and #172), and a first electrode and a second electrode adjacent to the gate electrode(#sd31/#sd32 for #T1 and #sd61/sd62 for #T6).
Kim does not disclose : the connection line and the substrate being spaced apart from each other by a first distance; the semiconductor layer and the substrate being spaced apart from each other by a second distance, wherein the second distance is different from the first distance.
However, in the same field of endeavor, Cha teaches : the connection line and the substrate being spaced apart from each other by a first distance(Fig 10a, #SP2 formed on #30); the semiconductor layer and the substrate being spaced apart from each other by a second distance(#TWL formed on #30), wherein the second distance is different from the first distance(Although #SP2 and #TWL are formed on the same layer, the distances from the substrate are different because of the non-planar profile of layer #30).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a connection line on a different layer than semiconductor layer, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Regarding claim 31, Kim as modified by Cha discloses : The display device of claim 30.
Kim teaches : wherein the first distance is shorter than the second distance such that the connection line is closer to the substrate than the semiconductor layer of either the first thin film transistor or the second thin film transistor(Fig. 5, #LK1 closer than #ACT6 to the substrate).
Regarding claim 32, Kim as modified by Cha discloses : The display device of claim 30.
Cha teaches : wherein the connection line and the semiconductor layer of the first thin film transistor and the second thin film transistor are on a same layer(connection line and semiconductor layer formed on same layer with different distances from the substrate because of the topography of the layer it is formed on [0203]).
Conclusion
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/D.T./Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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