DETAILED ACTION
General Remarks
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
3. When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
5. Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form
(http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(11) and Interview Practice for additional details.
6. Status of claim(s) to be treated in this office action:
a. Independent: 1, 10 and 18.
b. Pending: 1-20.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over EUGENIO PG PUB 20180136866 (hereinafter EUGENIO).
Regarding independent claim 1, EUGENIO teaches an apparatus (figure 1) comprising:
a first circuit (222 in figure 2, [0034], “…I/O 220 includes receiver (RX) 222 to receive data from the signal line for DQ0…”, 222 receives incoming write data, it can receive multiple sequential data sets) configured to receive a plurality of first write data (first data set) responsive to a first write command and then a plurality of second write data (second data set) responsive to a second write command following the first write command;
a second circuit (MUX228 in figure 2, [0035], “…I/O 220 includes multiplexer (mux) 228 to receive one or more phase outputs of DFE 224. The output of mux 228 can be synchronized to the DQS signal to provide the selected output to mux 230…”, or MUX440 in figure 4) coupled to the first circuit, the second circuit being configured to select one or ones of the plurality of first write data and one or ones of the plurality of second write data based, at least in part, on a first selection signal and a second selection signal following the first selection signal, respectively (there are some control signals that determines what the MUX outputs, at a first time (or during the first write data set) the control signal is in a first state[Wingdings font/0xE0] let us call it “first selection signal”, at a later time (e..g, for second write data set) the control signal is in a second state[Wingdings font/0xE0] let us call it “second selection signal”, [0035], “…I/O 220 includes multiplexer (mux) 228 to receive one or more phase outputs of DFE 224. The output of mux 228 can be synchronized to the DQS signal to provide the selected output to mux 230…”, or “first selection signal” could be initial configuration of the loopback MUX select bits for a first phase/setting, second selection signal could be reconfigured loopback mux select bits and a new loopback input is selected); and
a third circuit (loopback configuration logic/mode register/command programming logic that override write behavior and generate selection values for the multiplexers) configured to:
receive a second internal write command signal (loopback command flow from host) provided correspondingly to the second write command ([0029], “…host controller 110 includes loopback analysis 116 to perform loopback analysis on loopback data received from a memory component…Loopback analysis 116 can enable the host controller to evaluate the loopback data itself for signal integrity, or to evaluate the timing of the loopback signals, or the relative timing of loopback signal relative to the sending of a command…”) ;
mask a portion of the second internal write command signal (abstract, “…loopback circuitry to enable loopback of received data signals without having to access the data from the memory array…”) having a timing which partially overlaps a timing of the plurality of first write data to provide a masked second internal write command signal (WRSRTLB) (mode register/loopback configuration commands that “program the desired output”, [0048], “…the host can configure the memory device with mode register set commands or other configuration commands to program the desired output…”); and
provide the second selection signal (loopback configuration determining mux selection; multiple “different setting”, [0006], “…loopback process would typically be iterated multiple times with different phase settings (based on different settings for voltages, currents, termination, phase compensation (e.g., delay locked loops), and other settings, or a combination) until signaling settings are determined that can meet an expected bit error rate (BER)…”) based, at least in part, on the masked second internal command signal.
Regarding claim 2, EUGENIO teaches the apparatus of claim 1, wherein the second circuit is configured to select the one or ones of the plurality of first write data having a first phase when the first selection signal is in a first state and select the one or ones of the plurality of second write data having the first phase when the second selection signal is in the first state (EUGENIO teaches in [0035] “multiplexer (mux) 228 to receive one or more phase outputs of DFE 224. The output of mux 228 can be synchronized to the DQS signal to provide the selected output to mux 230 that can select an output to send on a feedback loop to the host controller”, [0006], “…loopback process would typically be iterated multiple times with different phase settings (based on different settings…”, therefore, EUGENIO teaches selecting data associated with a first phase, using a selection control for both first and second data sets).
Regarding claim 3, EUGENIO teaches the apparatus of claim 2, wherein the second circuit (MUX228 in figure 2, [0035], “…I/O 220 includes multiplexer (mux) 228 to receive one or more phase outputs of DFE 224. The output of mux 228 can be synchronized to the DQS signal to provide the selected output to mux 230…”, or MUX440 in figure 4) is configured to select the one or ones of the plurality of first write data having a second phase different from the first phase when the first selection signal is in a second state different from the first state and select the one or ones of the plurality of second write data having the second phase when the second selection signal is in the second state ([0006]/[0035], EUGENIO teaches selection among multiple phases, when selection logic is in first state[Wingdings font/0xE0] select one phase, when in second state[Wingdings font/0xE0]select another phase).
Regarding claim 4, EUGENIO teaches the apparatus of claim 3, wherein the second circuit is configured to select the one or ones of the plurality of first write data having the first phase when the first selection signal is in the first state and select the one or ones of the plurality of second write data having the second phase when the second selection signal is in the second state ([0006], [0035], “…loopback process would typically be iterated multiple times with different phase settings…”).
Regarding claim 5, EUGENIO teaches the apparatus of claim 4, wherein the second phase is different in 180° from the first phase ([0006], “…loopback process would typically be iterated multiple times with different phase settings…”, selecting a 180degree opposite phase is a straightforward, predictable choice in DDR timing calibration and therefore obvious under KSR).
Regarding claim 6, EUGENIO teaches the apparatus of claim 5, wherein the first circuit (222 in figure 2, [0034], “…I/O 220 includes receiver (RX) 222 to receive data from the signal line for DQ0…”, 222 receives incoming write data, it can receive multiple sequential data sets) is configured to latch the plurality of first write data and the plurality of second write data synchronously with an internal data strobe signal ([0044], “..I/O 420 includes receiver 422 to receive data from the signal line for DQ0. In one example, the input signal is sample against a reference signal VREF…”, [0033], “…DQS or data strobe signal can be applied to the various DQs…”)
Regarding claim 7, EUGENIO teaches the apparatus of claim 6, wherein the third circuit (loopback configuration logic/mode register/command programming logic that override write behavior and generate selection values for the multiplexers) is configured to make a state of the second selection signal different from a state of the first selection signal when a toggle count (“toggle count” has been interpreted as state counter, and [0006]/[0047] teaches the configurations between bursts have been repeatedly changed) of the internal data strobe signal in a period between an end time of receiving the plurality of first write data and a start time of receiving the plurality of second write data is odd numbered (EUGENIO teaches a loopback phase training uses a phase sweeps, iteration counts, and adjustment made between bursts based on sampling outcomes, changing selection based on an internal strobe-derived state is an obvious predictable control mechanism, using odd/even toggle counts for lane update is a standard strobe synchronized update method and is an obvious design choice inherent to strobe -based boundary detection).
Regarding claim 8, EUGENIO teaches the apparatus of claim 7, wherein the third circuit (loopback configuration logic/mode register/command programming logic that override write behavior and generate selection values for the multiplexers) is configured to make a state of the second selection signal same as a state of the first selection signal when a toggle count of the internal data strobe signal in the period is even numbered (EUGENIO teaches updating or not updating configuration based on observed strobe/phase information, when change criteria is not met, the training will maintains previous configuration).
Regarding claim 9, EUGENIO teaches the apparatus of claim 6, wherein the third circuit (loopback configuration logic/mode register/command programming logic that override write behavior and generate selection values for the multiplexers) is configured to decide a state of the second selection signal synchronously with the internal data strobe signal (EUGENIO teaches timing and phase selection decision based on strobe-derived sampling, see [0033]).
Regarding independent claim 10, EUGENIO teaches an apparatus (figure 1) comprising: a first circuit (222 in figure 2, [0034], “…I/O 220 includes receiver (RX) 222 to receive data from the signal line for DQ0…”, 222 receives incoming write data, it can receive multiple sequential data sets) configured to intermittently receive a plurality of write data sets each including a plurality of write data received in serial from outside responsive to a plurality of write commands, respectively (EUGENIO teaches external write commands providing write data into memory device, write data received serially on input DQ lines, multiple write commands arriving over time, leading to multiple write data sets, input buffer/data sampling circuitry receiving the incoming data);
a second circuit (MUX228 in figure 2, [0035], “…I/O 220 includes multiplexer (mux) 228 to receive one or more phase outputs of DFE 224. The output of mux 228 can be synchronized to the DQS signal to provide the selected output to mux 230…”, or MUX440 in figure 4) configured to select one or ones of the plurality of write data from each of the plurality of write data sets based on a selection signal and loopback the selected one or ones of the plurality of write data to outside (EUGENIO teaches MUX selects one write-data among several internal data lanes. The selected data is delivered to the output buffer for external loopback); and
a third circuit (loopback configuration logic/mode register/command programming logic that override write behavior and generate selection values for the multiplexers) configured to generate the selection signal, wherein the third circuit is configured to prevent a value of the selection signal from changing while the first circuit receives any of the plurality of write data sets (EUGENIO teaches a write burst corresponds to one write-data set, during burst, the selection signal remains stable so the same lane/path is used for the entire incoming data set, the selection signal only updates between bursts (e.g., not while receiving data)).
Regarding claim 11, EUGENIO teaches the apparatus of claim 10, wherein the first circuit is configured to receive the plurality of write data of each of the plurality of write data sets synchronously with a data strobe signal, and wherein the third circuit is configured to change the value of the selection signal synchronously with the data strobe signal ([0044], “..I/O 420 includes receiver 422 to receive data from the signal line for DQ0. In one example, the input signal is sample against a reference signal VREF…”, [0033], “…DQS or data strobe signal can be applied to the various DQs…”, EUGENIO teaches data DQ sampling in sync with DQS during write operation, the selection signal is updated in sync with the same strobe timing, because selection signal change occurs at write boundary timing governed by the internal strobe /timing generator).
Regarding claim 12, EUGENIO teaches the apparatus of claim 11, wherein the third circuit (loopback configuration logic/mode register/command programming logic that override write behavior and generate selection values for the multiplexers) is configured to change the value of the selection signal synchronously with the data strobe signal when an enable signal is in an active state (EUGENIO teaches the selection signal is updated in sync with the strobe timing, only get updated when the device allowed to switch data paths (e.g., at training enable, lane selection enable, burst boundary). “enable signal” is interpreted as “selection update allowed”).
Regarding claim 13, EUGENIO teaches the apparatus of claim 12, wherein the enable signal is brought into an active state each time the first circuit finishes receiving the plurality of write data sets (EUGENIO teaches during a write burst, selection cannot change, when a burst finishes, the controller transition to next burst boundary, at that moment, selection update is permitted, meaning enable signal active after reception completes).
Regarding claim 14, EUGENIO teaches the apparatus of claim 13, wherein the plurality of write data sets includes a first plurality of write data sets supplied responsive to a first occurrence of the write command and a second plurality of write data sets supplied responsive to a second occurrence of the write command, and wherein the third circuit (loopback configuration logic/mode register/command programming logic that override write behavior and generate selection values for the multiplexers) is configured to change the state of the selection signal after the first circuit finishes receiving the first plurality of write data sets and before the first circuit starts receiving the second plurality of write data sets (EUGENIO teaches each write command produces a write burst, selection signal is fixed during burst and may be updated between bursts).
Regarding claim 15, EUGENIO teaches the apparatus of claim 14, further comprising a fourth circuit (“timing controller”, timing controller initiates internal write timing (write start) associates with a new write command prior to actual data arrival) configured to activate a write start signal responsive to the second occurrence of the write command before the first circuit starts receiving the second plurality of write data, wherein the third circuit is configured to activate the enable signal under a condition that the write start signal is in an active state (EUGENIO teaches when internal write-stat timing is active, the lane selection enable or control logic transitions to a state where selection signal update is allowed).
Regarding claim 16, EUGENIO teaches the apparatus of claim 15, wherein the third circuit (loopback configuration logic/mode register/command programming logic that override write behavior and generate selection values for the multiplexers) is configured to bring the enable signal into an inactive state even if the write start signal is in an active state until the first circuit finishes receiving the first plurality of write data (EUGENIO teaches when there is ongoing burst reception, even if a new write command arrives internally (write-start active), selection signal will not change. The selection signal is fixed until the current burst ends).
Regarding claim 17, EUGENIO teaches the apparatus of claim 14, wherein the first circuit (222 in figure 2, [0034], “…I/O 220 includes receiver (RX) 222 to receive data from the signal line for DQ0…”, 222 receives incoming write data, it can receive multiple sequential data sets) is configured to receive the data strobe signal to generate an internal data strobe signal, and wherein the third circuit (loopback configuration logic/mode register/command programming logic that override write behavior and generate selection values for the multiplexers) is configured to change the state of the selection signal when a toggle count (“toggle count” has been interpreted as state counter, and [0006]/[0047] teaches the configurations between bursts have been repeatedly changed) of the internal data strobe signal in a period between an end time of receiving the first plurality of write data and a start time of receiving the second plurality of write data is odd numbered (internal strobe are derived from the external data strobe, selection signal update timing is controlled by strobe-driven internal counter/state machines, selection update occurs at defined internal strobe edges or at boundary toggles, using odd/even toggle counts for lane update is a standard strobe synchronized update method and is a obvious design choice inherent to strobe -based boundary detection).
Regarding independent claim 18, EUGENIO teaches an apparatus (figure 1) comprising:
a first circuit (222 in figure 2, [0034], “…I/O 220 includes receiver (RX) 222 to receive data from the signal line for DQ0…”, 222 receives incoming write data, it can receive multiple sequential data sets) configured to receive a first plurality of write data (first data set) in a first period and receive a second plurality of write data (second data set) in a second period after the first period;
a second circuit (MUX228 in figure 2, [0035], “…I/O 220 includes multiplexer (mux) 228 to receive one or more phase outputs of DFE 224. The output of mux 228 can be synchronized to the DQS signal to provide the selected output to mux 230…”, or MUX440 in figure 4) configured to activate an enable signal in a third period between the first period and the second period (the lane selection update is allowed only between write burst, this corresponds to an enable windown controlled by internal timing logic); and
a third circuit (loopback configuration logic/mode register/command programming logic that override write behavior and generate selection values for the multiplexers) configured to change a state of a selection signal indicating a phase of the second plurality of write data under a condition that the enable signal is in an active state, wherein the second circuit (MUX228 in figure 2, [0035], “…I/O 220 includes multiplexer (mux) 228 to receive one or more phase outputs of DFE 224. The output of mux 228 can be synchronized to the DQS signal to provide the selected output to mux 230…”, or MUX440 in figure 4) is configured to prevent the enable signal from activating in the first period (EUGENIO teaches during a write burst, selection cannot change, when a burst finishes, the controller transition to next burst boundary, at that moment, selection update is permitted, meaning enable signal active after reception completes).
Regarding claim 19, EUGENIO teaches the apparatus of claim 18, wherein each of the first and second plurality of write data are supplied synchronously with a data strobe signal ([0044], “..I/O 420 includes receiver 422 to receive data from the signal line for DQ0. In one example, the input signal is sample against a reference signal VREF…”, [0033], “…DQS or data strobe signal can be applied to the various DQs…”, EUGENIO teaches data DQ sampling in sync with DQS during write operation, the selection signal is updated in sync with the same strobe timing, because selection signal change occurs at write boundary timing governed by the internal strobe /timing generator).
Regarding claim 20, EUGENIO teaches the apparatus of claim 19, wherein the third circuit (loopback configuration logic/mode register/command programming logic that override write behavior and generate selection values for the multiplexers) is configured to activate the selection signal synchronously with the data strobe signal (EUGENIO teaches data DQ sampling in sync with DQS during write operation, the selection signal is updated in sync with the same strobe timing, because selection signal change occurs at write boundary timing governed by the internal strobe /timing generator).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XIAOCHUN L CHEN whose telephone number is (571)272-0941. The examiner can normally be reached on M-F: 9AM-5:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached on 571-272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/XIAOCHUN L CHEN/Examiner, Art Unit 2824