DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: the Amendment filed May 8, 2026.
Claims 1-20 are pending. Claims 1, 9 and 17 are independent.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement (IDS) filed on May 8, 2026. This IDS has been considered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 9-12 and 17-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Srinivasan et al. (U.S. 2018/0203774; hereinafter “Srinivasan”).
Regarding independent claim 1, Srinivasan discloses a memory device (Fig. 1) comprising:
a memory array (Fig. 1: 28); and
control logic (Fig. 1: 32), operatively coupled with the memory array (Fig. 1: 28), to perform operations comprising:
performing concurrent sensing operations on a set of two or more memory cells in a block of the memory array during a program verify phase of a program operation to determine whether each memory cell in the set of two or more memory cells was programmed to at least a program verify voltage during a program phase of the program operation (see page 3, par. 0034);
tracking a total number of cells in the set of memory cells that were not programmed to at least the program verify voltage during the program phase of the program operation (see page 3, par. 0035); and
determining, based on the total number of cells in the set of memory cells that were not programmed to at least the program verify voltage, whether the block of the memory array has passed the program verify phase of the program operation (see page 4, par. 0043).
Regarding claim 2, Srinivasan discloses wherein the control logic is to perform operations further comprising:
performing the program phase of the program operation (see page 3, par. 0034); and
initiating the program verify phase of the program operation in response to completion of the program phase of the program operation (see page 3, par. 0034).
Regarding claim 3, Srinivasan discloses wherein the set of two or more memory cells is associated with adjacent sub-blocks of the block of the memory array (see page 4, par. 0040 and 0043).
Regarding claim 4, Srinivasan discloses wherein the set of two or more memory cells is associated with different respective memory strings of the memory array (Operations are performed in multiple planes, see pages 1-2, par. 0008 and par. 0014. Fig. 1 shows a plurality of bit lines within different planes).
Regarding independent claim 9, Srinivasan discloses a method comprising:
performing concurrent sensing operations on a set of two or more memory cells in a block of a memory array of a memory device during a program verify phase of a program operation to determine whether each memory cell in the set of two or more memory cells was programmed to at least a program verify voltage during a program phase of the program operation (see page 3, par. 0034);
tracking a total number of cells in the set of memory cells that were not programmed to at least the program verify voltage during the program phase of the program operation (see page 3, par. 0035); and
determining, based on the total number of cells in the set of memory cells that were not programmed to at least the program verify voltage, whether the block of the memory array has passed the program verify phase of the program operation (see page 4, par. 0043).
Regarding claim 10, Srinivasan discloses performing the program phase of the program operation (see page 3, par. 0034); and
initiating the program verify phase of the program operation in response to completion of the program phase of the program operation (see page 3, par. 0034).
Regarding claim 11, Srinivasan discloses wherein the set of two or more memory cells is associated with adjacent sub-blocks of the block of the memory array (see page 4, par. 0040 and 0043).
Regarding claim 12, Srinivasan discloses wherein the set of two or more memory cells is associated with different respective memory strings of the memory array (Operations are performed in multiple planes, see pages 1-2, par. 0008 and par. 0014. Fig. 1 shows a plurality of bit lines within different planes).
Regarding independent claim 17, Srinivasan discloses a memory device (Fig. 1) comprising:
a memory array (Fig. 1: 28); and
control logic (Fig. 1: 32), operatively coupled with the memory array (Fig. 1: 28), to perform operations comprising:
performing concurrent sensing operations on a set of two or more memory cells in a block of the memory array during a program verify phase of a program operation to determine whether each memory cell in the set of two or more memory cells was programmed to at least a program verify voltage during a program phase of the program operation (see page 3, par. 0034);
tracking a total number of cells in the set of memory cells that were not programmed to at least the program verify voltage during the program phase of the program operation (see page 3, par. 0035); and
determining whether the total number of cells in the set of memory cells that were not programmed to at least the program verify voltage satisfies a verify threshold criterion (see page 3, par. 0035); and
in response to the total number of cells in the set of memory cells that were not programmed to at least the program verify voltage satisfying the verify threshold criterion, determining that the block of the memory array has passed the program verify phase of the program operation (see page 4, par. 0043).
Regarding claim 18, Srinivasan discloses wherein the set of two or more memory cells is associated with adjacent sub-blocks of the block of the memory array (see page 4, par. 0040 and 0043).
Regarding claim 19, Srinivasan discloses wherein the set of two or more memory cells is associated with different respective memory strings of the memory array (Operations are performed in multiple planes, see pages 1-2, par. 0008 and par. 0014. Fig. 1 shows a plurality of bit lines within different planes).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5, 13 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Srinivasan et al. (U.S. 2018/0203774; hereinafter “Srinivasan”) in view of Taito et al. (U.S. 2005/0057972; hereinafter “Taito”).
Regarding claim 5, Srinivasan discloses the limitations with respect to claim 4.
However, Srinivasan is silent with respect to concurrently activating a respective select gate device coupled between each respective memory string and a shared bit line of the memory array and sensing whether a current from the shared bitline flows through each respective memory string.
Taito teaches concurrently activating a respective select gate device coupled between each respective memory string (Fig. 11: 3-00 and 3-01 are high “H”) and a shared bit line of the memory array (Fig. 11: MBL0); and
sensing whether a current from the shared bitline flows through each respective memory string (Fig. 11: read current).
Since Taito and Srinivasan are from the same field of endeavor, the teachings described by Taito would have been recognized in the pertinent art of Srinivasan.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Taito with the teachings of Srinivasan for the purpose of prevent read speed from decreasing, see Taito’s page 15, par. 0181.
Regarding claim 13, Srinivasan discloses the limitations with respect to claim 12.
However, Srinivasan is silent with respect to concurrently activating a respective select gate device coupled between each respective memory string and a shared bit line of the memory array and sensing whether a current from the shared bitline flows through each respective memory string.
Taito teaches concurrently activating a respective select gate device coupled between each respective memory string (Fig. 11: 3-00 and 3-01 are high “H”) and a shared bit line of the memory array (Fig. 11: MBL0); and
sensing whether a current from the shared bitline flows through each respective memory string (Fig. 11: read current).
Since Taito and Srinivasan are from the same field of endeavor, the teachings described by Taito would have been recognized in the pertinent art of Srinivasan.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Taito with the teachings of Srinivasan for the purpose of prevent read speed from decreasing, see Taito’s page 15, par. 0181.
Regarding claim 20, Srinivasan discloses the limitations with respect to claim 19.
However, Srinivasan is silent with respect to concurrently activating a respective select gate device coupled between each respective memory string and a shared bit line of the memory array and sensing whether a current from the shared bitline flows through each respective memory string.
Taito teaches concurrently activating a respective select gate device coupled between each respective memory string (Fig. 11: 3-00 and 3-01 are high “H”) and a shared bit line of the memory array (Fig. 11: MBL0); and
sensing whether a current from the shared bitline flows through each respective memory string (Fig. 11: read current).
Since Taito and Srinivasan are from the same field of endeavor, the teachings described by Taito would have been recognized in the pertinent art of Srinivasan.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Taito with the teachings of Srinivasan for the purpose of prevent read speed from decreasing, see Taito’s page 15, par. 0181.
Allowable Subject Matter
Claims 6-8 and 14-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
With respect to claim 6, there is no teaching or suggestion in the prior art of record to provide the recited current from the shared bitline does not flow through each respective memory string if each memory cell in the set of memory cells was programmed to at least the program verify voltage during the program phase of the program operation.
With respect to claim 7, there is no teaching or suggestion in the prior art of record to provide the recited responsive to determining that each memory cell in the set of memory cells was not programmed to at least the program verify voltage during the program phase of the program operation, incrementing a value of a counter, and determining whether there are one or more additional sets of memory cells in the block of the memory array that were programmed during the program phase of the program operation.
With respect to claim 14, there is no teaching or suggestion in the prior art of record to provide the recited current from the shared bitline does not flow through each respective memory string if each memory cell in the set of memory cells was programmed to at least the program verify voltage during the program phase of the program operation.
With respect to claim 15, there is no teaching or suggestion in the prior art of record to provide the recited responsive to determining that each memory cell in the set of memory cells was not programmed to at least the program verify voltage during the program phase of the program operation, incrementing a value of a counter, and determining whether there are one or more additional sets of memory cells in the block of the memory array that were programmed during the program phase of the program operation.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant's arguments filed with respect to claim 1 have been fully considered but they are not persuasive.
With respect to independent claim 1, Applicant asserts that Srinivasan does not disclose concurrent sensing operations where two or more memory cells are sensed simultaneously during a single program verify phase because Srinivasan only describes sequential program and verify iteration in paragraph 0034, see Applicant’s Remarks page 8. This particular remark is not considered persuasive.
Srinivasan’s paragraph 0034 describes a verify operation for a plurality (“two or more”) of memory cells, and during a programming operation a plurality of program-verify operation are performed, wherein the verify operation acts in conjunction (“concurrently”) with the program pulse in a particular program loop to verify whether the target analog values have been reached.
Furthermore, Applicant asserts that Srinivasan does not disclose memory cells from different sub-blocks sharing a common bitline, nor does it disclose concurrently activating select gate devices to perform simultaneously sensing operations, see Applicant’s Remarks page 9.
This particular remark is not considered persuasive since it appears that is directed to subject matter not present in the claims. While raising an interesting point, claim 1 does not required different sub-blocks sharing a common bitline and/or concurrently activation of select gate devices.
For the above reasons, the previously applied rejections are considered proper and maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALFREDO BERMUDEZ LOZADA whose telephone number is (571)272-0877. The examiner can normally be reached 7:00AM-3:30PM EST.
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/Alfredo Bermudez Lozada/ Primary Examiner, Art Unit 2825
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