DETAILED ACTION
Claims 1-11 are pending.
The office acknowledges the following papers:
Claims and remarks filed on 10/29/2025.
Withdrawn objections and rejections
The specification objection has been withdrawn.
New Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 5-6, 8, and 11 are rejected under 35 U.S.C. 102(a)(1 & 2) as being anticipated by McDonald et al. (U.S. 2014/0244983).
As per claim 1:
McDonald disclosed a method for executing a function call, comprising:
receiving a first function call that identifies at least one function (McDonald: Figures 1-2 and 4 elements 106, 210-230, and 402, paragraphs 29-30, 40-41, 45, 47, and 60)(A scheduler receives a task (i.e. first function call) to schedule execution on a processor. The function table points to/branches to an address for execution of the function of the task to be performed by a given processor.);
storing an instruction packet in a memory of a main chip, wherein the instruction packet includes a list of main chip functions executable by the main chip and a list of one or more accelerator chip functions executable by an accelerator chip that has a different architecture than the main chip (McDonald: Figures 1-2 and 4-5 elements 106, 110-112, 202, 210-230, 404, 532, and 556, paragraphs 24-26, 30-31, 36, 40-41, 45, 47, 61, and 70)(The broadest reasonable interpretation of an “instruction packet that includes a list of main chip functions …” is ISA information/documentation based on specification paragraphs 16-18, which state an instruction packet “can be understood as an instruction set architecture (ISA)” … “may comprises the functions found in an ISA documentation.” ISA information/documentation for each processor is provided to selectively create function tables for the tasks when the task is supported by one or both of the primary CPU processor (i.e. main chip) and secondary DSP processor (i.e. accelerator chip). The primary and secondary processors have different architectures due to them not being able to support the same functions. A function call executable on either processor includes both main chip and accelerator chip operations. The memory stores both function tables and the set of functions representing a function call (i.e. instruction packet).);
determining that the at least one function identified by the first function call is included in the list of the main chip functions or the list of the one or more accelerator chip functions included in the instruction packet and/or can be composed of the main chip functions or the one or more accelerator chip functions included in the instruction packet (McDonald: Figures 1 and 4 elements 106 and 404, paragraphs 30-31 and 61)(The scheduler determines if the task is executable on both processor instruction sets (i.e. list of main/accelerator chip functions).); and
executing the function call by the main chip (McDonald: Figure 4 elements 406 and 410, paragraphs 30-31 and 60-61)(A task only executable on the CPU processor is executed by the CPU processor. A task can also be executed by the CPU processor when it meets a selection criteria of the scheduler.).
As per claim 5:
McDonald disclosed the method according to claim 1, wherein the first function call identifies at least one of the one or more accelerator chip functions included in the instruction packet (McDonald: Figures 1-2 and 4 elements 110-112, 210-230, and 404, paragraphs 24-26, 40-41, 45, 47, 61, and 66)(The received task can be executed on either processor for supported function calls. A second processor can be implemented as a GPU, DSP, ASIC, etc. (i.e. accelerator).).
As per claim 6:
Claim 6 essentially recites the same limitations of claim 1. Claim 6 additionally recites the following limitations:
a processor (McDonald: Figure 5 elements 510 and 574, paragraph 69); and
a memory storing a program (McDonald: Figure 5 elements 532 and 556, paragraph 70).
As per claim 8:
McDonald disclosed the system according to claim 6, wherein the main chip and/or the accelerator chip are/is a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a Digital Signal Processor (DSP), or an Application Specific Integrated Circuit (ASIC) (McDonald: Figure 1 elements 110-112, paragraphs 24-26 and 66).
As per claim 11:
Claim 11 essentially recites the same limitations of claim 1. Therefore, claim 11 is rejected for the same reasons as claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-4, 7, and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over McDonald et al. (U.S. 2014/0244983), in view of Official Notice.
As per claim 2:
McDonald disclosed the method according to claim 1, further comprising:
executing a second function call on the accelerator chip, wherein the second function call identifies at least one special function, and wherein the special function is not included in the instruction packet and/or cannot be composed of the main chip functions or the one or more accelerator chip functions included in the instruction packet (McDonald: Figures 1-2 and 4 elements 110-112, 210-230, and 404-406, paragraphs 24-26, 40-41, 45, 47, 61, and 66)(The received task can be executed on a single supported processor. A second processor can be implemented as a GPU, DSP, ASIC, etc. (i.e. accelerator). Official notice is given that accelerators include instruction sets not supported by the primary CPU for the advantage of accelerating special types of functions. Thus, it would have been obvious to one of ordinary skill in the art to implement executing a task on the accelerator of McDonald when the task is only supported by the accelerator.).
As per claim 3:
McDonald disclosed the method according to claim 2, wherein the executing the second function call takes place on the accelerator chip parallel in time and/or after executing the second function call on the main chip (McDonald: Figures 1 and 4 elements 106, 110-114, 406, and 410, paragraphs 24-26, 30-31, 34, and 60-61)(Parallel tasks can be executed on the two processors.).
As per claim 4:
McDonald disclosed the method according to claim 2, further comprising:
communicating, by the main chip, with the accelerator chip via an interprocessor communication protocol that is integrated into the main chip (McDonald: Figure 1 elements 106 and 120, paragraphs 30-31 and 33)(Official notice is given that accelerated tasks return execution results to a main processor for the advantage of allowing the main processor to further process execution results. Thus, it would have been obvious to one of ordinary skill in the art to implement returning execution results from a task scheduled on the DSP/GPU/ASIC to the main CPU.).
As per claim 7:
The additional limitation(s) of claim 7 basically recite the additional limitation(s) of claim 2. Therefore, claim 7 is rejected for the same reason(s) as claim 2.
As per claim 9:
McDonald disclosed the system according to claim 8, wherein the ASIC is a Machine Learning ASIC (McDonald: Figures 1 and 4 elements 110-112, paragraph 66)(Official notice is given that ASICs can implement machine learning operations for the advantage of allowing custom operations with increased performance. Thus, it would have been obvious to one of ordinary skill in the art to implement machine learning operations in the ASIC of McDonald.).
As per claim 10:
McDonald disclosed the system according to claim 8, wherein the CPU has an x86 architecture, an ARM architecture, a Reduced Instruction Set Computer, fifth version (RISC-V) architecture, or a Microprocessor without Interlocked Pipeline Stages (MIPS) architecture (McDonald: Figure 1 element 110, paragraph 24)(Official notice is given that CPUs implement x86/RISC-V/MIPS for the advantage of providing common ISAs for data processing. Thus, it would have been obvious to one of ordinary skill in the art to implement x86/RISC-V/MIPS as the specific ISA of the CPU.).
Response to Arguments
The arguments presented by Applicant in the response, received on 10/29/2025 are not considered persuasive.
Applicant argues for claim 1:
“Paragraph [0023] of McDonald teaches that, in the system 100 of FIG. 1, an operating system (O/S) 104 and components/applications associated therewith may be concurrently executed on a first processor 110 having a first ISA and a second processor 112 having a second ISA. Nothing has been found, or pointed to, in McDonald which teaches or suggests that a memory of the first processor 110 stores an instruction packet that includes a list of chip functions executable by the first processor 110 and a list of one or more chip functions executable by the second processor 112 and/or that a memory of the second processor 112 stores an instruction packet that includes a list of chip functions executable by the second processor 112 and a list of one or more chip functions executable by the first processor 110.”
This argument is not found to be persuasive for the following reason. McDonald shows in figure 2 a memory that stores various addresses of function calls. The branching to the function calls includes instructions that are executable on a given processor. The storage of the corresponding functions for a given task executable in the primary and secondary processor reads upon the amended instruction packet.
Applicant argues for claim 6:
“Although the language and scope of independent claim 6 differ from that of independent claim 1, the allowability of independent claim 6 will be apparent in view of the above discussion. For example, claim 6 is directed to a system and, as amended, recites, among other things, "a memory storing a program that, when executed by [a] processor, cause [a] main chip to ... store an instruction packet in the memory of the main chip, wherein the instruction packet includes a list of main chip functions executable by the main chip and a list of one or more accelerator chip functions executable by an accelerator chip that has a different architecture than the main chip." As can be appreciated from the discussion above, the cited reference fails to teach or suggest a system having such features.”
This argument is not found to be persuasive for the following reason. The memory of McDonald includes storage for the OS, OS scheduler, and functions that causes the primary claimed limitations to be read upon. Thus, reading upon the claimed limitations.
Applicant argues for claim 11:
“Although the language and scope of independent claim 11 differ from that of independent claim 1, the allowability of independent claim 11 will be apparent in view of the above discussion. For example, claim 11 is directed to a non-transitory computer-readable medium and, as amended, recites, among other things, "a program that, when executed by a processor, causes a main chip to ... store an instruction packet in a memory of the main chip, wherein the instruction packet includes a list of main chip functions executable by the main chip and a list of one or more accelerator chip functions executable by an accelerator chip that has a different architecture than the main chip." As can be appreciated from the discussion above, the cited reference fails to teach or suggest a computer-readable medium having such features.”
This argument is not found to be persuasive for the following reason. The memory of McDonald includes storage for the OS, OS scheduler, and functions that causes the primary claimed limitations to be read upon.
Applicant’s arguments rely on language solely recited in preamble recitations in claim 11. When reading the preamble in the context of the entire claim, the recitation of the medium storing an executable program is not limiting because the body of the claim describes a complete invention and the language recited solely in the preamble does not provide any distinct definition of any of the claimed invention’s limitations. Thus, the preamble of the claim(s) is not considered a limitation and is of no significance to claim construction. See Pitney Bowes, Inc. v. Hewlett-Packard Co., 182 F.3d 1298, 1305, 51 USPQ2d 1161, 1165 (Fed. Cir. 1999). See MPEP § 2111.02.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The following is text cited from 37 CFR 1.111(c): In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB A. PETRANEK whose telephone number is (571)272-5988. The examiner can normally be reached on M-F 8:00-4:30.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on (571) 270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACOB PETRANEK/Primary Examiner, Art Unit 2183