DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-15 in the reply filed on 08/14/2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 and 5 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nakamura et al. (US 6756262 B1, hereinafter Nakamura)
With regards to claim 1, Nakamura discloses a semiconductor device, (FIG. 19) comprising:
a substrate; (substrate 1)
multiple core components (components comprising at least source/drain 17) formed in the substrate and comprising active areas; (See FIG. 19)
multiple contact plugs (plugs 20) formed on the core components in an interlayer dielectric layer; (SiO film 16/21)
multiple edge contact pads (pads 39) on parts of the contact plugs in the interlayer dielectric layer, wherein at least two of the contact plugs and the edge contact pads are integrally-formed; (see FIG. 19, showing layers integral to each other) and
multiple capacitors (capacitors 45-49) formed on the interlayer dielectric layer, and parts of the capacitors with bottoms contacting the edge contact pads. (See FIG. 19)
With regards to claim 2, Nakamura discloses the semiconductor device of claim 1, wherein the substrate comprises a core region (region comprising capacitors 45-49) with a boundary (region on the edge of the capacitors 45-49) and a central region, and the core components are formed in the core region, and a bottom of each of the contact plugs contacts the active area of the corresponding core component. (see FIG. 19, showing the contact)
With regards to claim 5, Nakamura discloses a semiconductor device of claim 2, further comprising:
multiple word lines, (word line WL) each of the word lines intersects the active areas in the core region;
multiple bit lines, (bit line BL) wherein an extending direction of the bit lines is perpendicular to an extending direction of the word lines; (See FIGS. 1 -19) and
wherein the edge contact pad crosses over at least one of the word lines. (see at least FIG. 19, where the pads 39 are over the word lines WL)
Allowable Subject Matter
Claims 7-15 are allowed.
Claims 3-4 and 6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Han et al. (US 8928092 B2) – memory device
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN M Page whose telephone number is (571)272-3249. The examiner can normally be reached M-F: 10:00AM-6:00PM.
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/STEVEN M PAGE/Primary Patent Examiner, Art Unit 2812
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