Prosecution Insights
Last updated: October 22, 2026
Application No. 18/780,534

APPARATUS AND METHOD FOR SUBSTRATE HANDLING

Non-Final OA §102§103
Filed
Jul 23, 2024
Priority
Mar 31, 2021 — provisional 63/168,264 +1 more
Examiner
GATES, ERIC ANDREW
Art Unit
3722
Tech Center
3700 — Mechanical Engineering & Manufacturing
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
79%
Grant Probability
Favorable
1-2
OA Rounds
6m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allowance Rate
879 granted / 1116 resolved
+8.8% vs TC avg
Moderate +15% lift
Without
With
+14.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
51 currently pending
Career history
1162
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
41.6%
+1.6% vs TC avg
§102
32.4%
-7.6% vs TC avg
§112
20.2%
-19.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1116 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Election/Restrictions Applicant’s election without traverse of Invention I, Species 3Di, claims 1-6 and 8-10 in the reply filed on 17 June 2026 is acknowledged. Claim 7 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 17 June 2026. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-6, 8, and 11-19 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ishino et al. (US 2018/0193983 A1). Regarding claim 1, Ishino et al. discloses a method for handling a semiconductor substrate W comprising: placing a semiconductor substrate W over a semiconductor apparatus 1, wherein: a central portion of the semiconductor substrate overlies a carrying surface (upper surface of chuck table 1) of a chuck table 1 of the semiconductor apparatus, an edge portion of the semiconductor substrate overlies a top surface 222 of a first flexible member 22 (see figure 3A) of the semiconductor apparatus, the first flexible member is disposed within a recess 12 of the chuck table and extends along a perimeter of the carrying surface, and a gap (see figure 2) forms among the semiconductor substrate, the carrying surface of the chuck table, and the top surface of the first flexible member (see figure 2); and introducing a vacuum in vacuum holes 101/102 in the chuck table to form a vacuum seal among the semiconductor substrate, the chuck table, and the first flexible member. Regarding claim 2, Ishino et al. discloses wherein the first flexible member 22 comprises a first portion 221 and a second portion 222 connected to the first portion, the first portion extends along a direction parallel to the carrying surface (along W21 in figure 3A) and comprises opposing sidewalls physically connected to inner sidewalls 121 of the chuck table (see figure 3A), the second portion comprises a top surface 222 protruded from the recess before forming the vacuum seal (see figure 3A). Regarding claim 3, Ishino et al. discloses wherein after forming the vacuum seal, the first flexible member 22 is compressed as the semiconductor substrate presses against the top surface of the second portion 222 of the first flexible member. Regarding claim 4, Ishino et al. discloses wherein an angle between the first portion 221 and the second portion 222 of the first flexible member 22 reduces when forming the vacuum seal (when portion 222 is accommodated in second groove portion 122). Regarding claim 5, Ishino et al. discloses wherein when introducing the vacuum in the vacuum holes 101/102 in the chuck table 1: contacting the central portion of the semiconductor substrate W with the carrying surface (upper surface of chuck table 1) of the chuck table to form a seal between the semiconductor substrate and the carrying surface; and deforming the first flexible member 22 by pressing the edge portion of the semiconductor substrate against the first flexible member through a downward force created by the vacuum to form the vacuum seal between the semiconductor substrate and the first flexible member. Regarding claim 6, Ishino et al. discloses wherein when introducing the vacuum in the vacuum holes 101/102 in the chuck table: flattening the semiconductor substrate W; and leveling the top surface 222 of the first flexible member 22 with the carrying surface (upper surface of chuck table 1) of the chuck table (when portion 222 is accommodated in second groove portion 122). Regarding claim 8, Ishino et al. discloses wherein a passageway (Each of the first air passage 101 and the second air passage 102 is formed of a through hole extending in a top-to-bottom direction of the base 1 and may also be formed of a passage extending inside the base 1 or a groove extending along the lower surface (back surface) of the base 1. In the case where the groove is formed along the lower surface of the base 1, the groove constitutes a part of the air passage when the base 1 is joined to the upper surface of a pedestal (not illustrated)) is in the chuck table 1 and connected to a vacuum source, each of the vacuum holes 101/102 extends between the carrying surface (upper surface of chuck table 1) of the chuck table and the passageway, during introducing the vacuum in the vacuum holes in the chuck table, creating a suction force through the vacuum holes and the passageway, wherein the suction force pulls the semiconductor substrate W against the carrying surface 10 of the chuck table in a downward direction. Regarding claim 11, Ishino et al. discloses a method for handling a semiconductor substrate W, comprising: placing a semiconductor substrate over a semiconductor apparatus 1, wherein: the semiconductor apparatus comprises a chuck table 1 having a carrying surface (upper surface of chuck table 1) and comprising vacuum holes 101/102 extending from the carrying surface, and a flexible member 22 extending along a periphery of the chuck table, the flexible member comprises a lower portion 221 engaged with the chuck table and an upper portion 222 connected to the lower portion, an acute angle is between a lower surface of the upper portion and an upper surface of the lower portion facing and separated from the lower surface of the upper portion (see figure 3A); and forming a vacuum seal between the semiconductor substrate and the chuck table by using the flexible member serving as a sealing ring, wherein when forming the vacuum seal, the upper portion of the flexible member is changed from a position higher than the carrying surface to a position substantially leveled with the carrying surface (when portion 222 is accommodated in second groove portion 122). Regarding claim 12, Ishino et al. discloses wherein after placing the semiconductor substrate W over the semiconductor apparatus 1, an edge portion of the semiconductor substrate is in contact with the upper portion 222 of the flexible member 22, and a central portion of the semiconductor substrate is in contact with the carrying surface (upper surface of chuck table 1) of the chuck table 1. Regarding claim 13, Ishino et al. discloses further comprising: providing the semiconductor substrate W, wherein the semiconductor substrate is warped with a central portion of the semiconductor substrate lower than an edge portion of the semiconductor substrate (see figure 3A). Regarding claim 14, Ishino et al. discloses wherein the acute angle of the flexible member 22 reduces when forming the vacuum seal (when portion 222 is accommodated in second groove portion 122). Regarding claim 15, Ishino et al. discloses wherein a passageway (Each of the first air passage 101 and the second air passage 102 is formed of a through hole extending in a top-to-bottom direction of the base 1 and may also be formed of a passage extending inside the base 1 or a groove extending along the lower surface (back surface) of the base 1. In the case where the groove is formed along the lower surface of the base 1, the groove constitutes a part of the air passage when the base 1 is joined to the upper surface of a pedestal (not illustrated)) is in the chuck table 1 and in communication with each of the vacuum holes 101/102, forming the vacuum seal comprises: applying a suction force through the passageway and the vacuum holes to pull the semiconductor substrate W. Regarding claim 16, Ishino et al. discloses a method for handling a semiconductor substrate W, comprising: placing a semiconductor substrate over a semiconductor apparatus 1, wherein a first flexible member 22 of the semiconductor apparatus is disposed in a first recess 12 provided within a carrying surface (upper surface of chuck table 1) of a chuck table 1 of the semiconductor apparatus, and the first flexible member comprises: a lower portion 221 comprising opposing sidewalls and a bottom surface that are in contact with inner surfaces 121 of the chuck table (see figure 3A); and an upper portion 222 comprising a fixed end and a free end (see figure 3A), wherein an included angle between the free end and the lower portion is an acute angle (see figure 3A), the fixed end is connected to the lower portion and in contact with the chuck table (see figure 3A), and the free end is positioned opposite the fixed end; and forming a vacuum seal between the semiconductor substrate and the chuck table, wherein when forming the vacuum seal, the semiconductor substrate presses against the upper portion of the first flexible member. Regarding claim 17, Ishino et al. discloses wherein when placing the semiconductor substrate W over the semiconductor apparatus 1, the free end of the upper portion 222 of the first flexible member 22 is in contact with the edge portion of the semiconductor substrate. Regarding claim 18, Ishino et al. discloses wherein when placing the semiconductor substrate W over the semiconductor apparatus 1, the carrying surface (upper surface of chuck table 1) of the chuck table is in contact with the central portion of the semiconductor substrate. Regarding claim 19, Ishino et al. discloses wherein: a passageway (Each of the first air passage 101 and the second air passage 102 is formed of a through hole extending in a top-to-bottom direction of the base 1 and may also be formed of a passage extending inside the base 1 or a groove extending along the lower surface (back surface) of the base 1. In the case where the groove is formed along the lower surface of the base 1, the groove constitutes a part of the air passage when the base 1 is joined to the upper surface of a pedestal (not illustrated)) is in the chuck table 1 and extends in a direction substantially parallel to the carrying surface (upper surface of chuck table 1), and vacuum holes 101/102 extend between the carrying surface and the passageway, when forming the vacuum seal, a suction force is applied through the passageway and the vacuum holes. Claims 1, 5-6, 11-12, and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kikuchi et al. (WO 2017/086333 A1). Regarding claim 1, Kikuchi et al. discloses a method for handling a semiconductor substrate W comprising: placing a semiconductor substrate W over a semiconductor apparatus 1, wherein: a central portion of the semiconductor substrate overlies a carrying surface (a plurality of substantially cylindrical, substantially hemispherical or substantially truncated cone shaped pins formed in the area surrounded by sealing members 2 and 2’ in figure 7, pins not shown) of a chuck table 1 of the semiconductor apparatus, an edge portion of the semiconductor substrate overlies a top surface 22 of a first flexible member 2’ (embodiment of figures 2-3) of the semiconductor apparatus, the first flexible member is disposed within a recess 10 of the chuck table and extends along a perimeter of the carrying surface, and a gap (see figure 2) forms among the semiconductor substrate, the carrying surface of the chuck table, and the top surface of the first flexible member (see figure 2); and introducing a vacuum in vacuum holes 102/102’ in the chuck table to form a vacuum seal among the semiconductor substrate, the chuck table, and the first flexible member. Regarding claim 5, Kikuchi et al. discloses wherein when introducing the vacuum in the vacuum holes 102/102’ in the chuck table: contacting the central portion of the semiconductor substrate W with the carrying surface (pins) of the chuck table to form a seal between the semiconductor substrate and the carrying surface; and deforming the first flexible member 2’ by pressing the edge portion of the semiconductor substrate against the first flexible member through a downward force created by the vacuum to form the vacuum seal between the semiconductor substrate and the first flexible member. Regarding claim 6, Kikuchi et al. discloses wherein when introducing the vacuum in the vacuum holes 102/102’ in the chuck table 1: flattening the semiconductor substrate W; and leveling the top surface 22 of the first flexible member 2’ with the carrying surface (pins) of the chuck table. Regarding claim 11, Kikuchi et al. discloses a method for handling a semiconductor substrate W, comprising: placing a semiconductor substrate over a semiconductor apparatus 1, wherein: the semiconductor apparatus comprises a chuck table 1 having a carrying surface (a plurality of substantially cylindrical, substantially hemispherical or substantially truncated cone shaped pins formed in the area surrounded by sealing members 2 and 2’ in figure 7, pins not shown) and comprising vacuum holes 102/102’ extending from the carrying surface, and a flexible member 2’ extending along a periphery of the chuck table, the flexible member comprises a lower portion 21 engaged with the chuck table and an upper portion 22 connected to the lower portion, an acute angle (see figure 2) is between a lower surface of the upper portion and an upper surface of the lower portion facing and separated from the lower surface of the upper portion; and forming a vacuum seal between the semiconductor substrate and the chuck table by using the flexible member serving as a sealing ring, wherein when forming the vacuum seal, the upper portion of the flexible member is changed from a position higher than the carrying surface to a position substantially leveled with the carrying surface (see figure 3). Regarding claim 12, Kikuchi et al. discloses wherein after placing the semiconductor substrate W over the semiconductor apparatus 1, an edge portion of the semiconductor substrate is in contact with the upper portion 22 of the flexible member 2’ (see figure 3), and a central portion of the semiconductor substrate is in contact with the carrying surface (pins) of the chuck table. Regarding claim 14, Kikuchi et al. discloses wherein the acute angle of the flexible member 2’ reduces when forming the vacuum seal (see figures 2-3). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 9 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ishino et al. (US 2018/0193983 A1) in view of Otwell (US 6,196,532). Regarding claim 9, Ishino et al. discloses the invention substantially as claimed, except Ishino et al. does not disclose wherein the chuck table further comprises slot openings recessed from the carrying surface and in communication with the vacuum holes, second flexible members of the semiconductor apparatus are disposed within the slot openings and surround the vacuum holes, and during introducing the vacuum in the vacuum holes in the chuck table, the second flexible members are compressed as the semiconductor substrate presses against the second flexible members. Otwell teaches the use of a vacuum chuck 100 for handling a semiconductor substrate, the chuck comprising a vacuum table 104 having slot openings 110 with vacuum holes 118 and flexible members 102 that are disposed within the slot openings and surround the vacuum holes such that during introducing a vacuum in the vacuum holes in the chuck table, the flexible members are compressed as the semiconductor substrate presses against the second flexible members for the purpose of creating a vacuum to hold the semiconductor substrate. Therefore, it would have been obvious to one having ordinary skill in the art prior to the effective filing date of the invention to have combined the chuck table of Ishino et al. with the second flexible members surrounding vacuum hole as taught by Otwell in order to provide additional sealing of the semiconductor substate to the chuck table at the vacuum holes. Regarding claim 20, Ishino et al. discloses the invention substantially as claimed, except Ishino et al. does not disclose wherein the chuck table further comprises second recesses arranged along a perimeter of the carrying surface and surrounded by the first recess, and second flexible members of the semiconductor apparatus are disposed in the second recesses in a one-to-one correspondence, when forming the vacuum seal, the second flexible members are compressed by the semiconductor substrate. Otwell teaches the use of a vacuum chuck 100 for handling a semiconductor substrate, the chuck comprising a vacuum table 104 having recesses 110 with vacuum holes 118 and flexible members 102 that are disposed within the recesses in a one-to-one correspondence and surround the vacuum holes such that during introducing a vacuum in the vacuum holes in the chuck table, the flexible members are compressed as the semiconductor substrate presses against the second flexible members for the purpose of creating a vacuum to hold the semiconductor substrate. Therefore, it would have been obvious to one having ordinary skill in the art prior to the effective filing date of the invention to have combined the chuck table of Ishino et al. with the second flexible members surrounding vacuum hole as taught by Otwell in order to provide additional sealing of the semiconductor substate to the chuck table at the vacuum holes. Allowable Subject Matter Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Ben Natan et al. (US 2017/0053822 A1) discloses a method for handling a semiconductor substrate using a chuck table with a vacuum and a flexible sealing member. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC ANDREW GATES whose telephone number is (571)272-5498. The examiner can normally be reached on M-Th 9-6, Alt Fr 9-5. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sunil Singh, can be reached on 571-272-3460. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERIC A. GATES/Primary Examiner, Art Unit 3722 28 September 2026
Read full office action

Prosecution Timeline

Jul 23, 2024
Application Filed
Oct 01, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
79%
Grant Probability
93%
With Interview (+14.6%)
2y 9m (~6m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1116 resolved cases by this examiner. Grant probability derived from career allowance rate.

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