DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 - 8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamazaki et al. (7982250).
With regard to claim 1, Yamazaki et al. disclose a semiconductor device (for example, see fig. 2A), comprising:
a stacked transistor structure having field effect transistors (for example, transistors 210, 231) on at least two levels (referred to as “A1” and “A2” by examiner’s annotation shown in fig. 2A below);
active regions (119, 208a, 208b, 216, 220a, 220b wherein the regions 208b, 220a are annotated below) longitudinally disposed on each of the at least two levels (A1, A2), the active regions (119, 208a, 208b, 216, 220a, 220b) including source/drain regions (208a, 208b, 220a, 220b) and channel regions (119, 216);
at least one active region (216, 220a, 220b; 119, 208a, 208b; or 208a, 220b) of the active regions (119, 208a, 208b, 216, 220a, 220b) includes a transition region (referred to as “216A1” by examiner’s annotation shown in fig. 2A below; wherein the transition region 216A1 is a portion of the channel region 216) wherein longitudinal portions (220b, 220a; or 208a, 208b; or 208a, 220b) of the at least one active region (216, 220a, 220b; or 208a, 208b, 119) are laterally offset within a same level (for example, a same level A1, A2) by the transition region (216A1 or 119) to provide an offset space (referred to as “S1” by examiner’s annotation shown in fig. 2A below); and
the offset space (S1) including a vertical interconnect (referred to as “S1” by examiner’s annotation shown in fig. 2A below).
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With regard to claim 2, Yamazaki et al. disclose the transition region (216A1) is disposed within a channel region (referred to as “216B1” by examiner’s annotation shown in fig. 2A below) of the channel regions (referred to as “216B1 “216B2” by examiner’s annotation shown in fig. 2A below).
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With regard to claim 3, Yamazaki et al. disclose the vertical interconnect (240A1) includes a middle (referred to as “240A2” by examiner’s annotation shown in fig. 2A below) of the line contact (referred to as “240A3” by examiner’s annotation shown in fig. 2A below).
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With regard to claim 4, Yamazaki et al. disclose the vertical interconnect (240A1) includes a backside contact (referred to as “240A4” by examiner’s annotation shown in fig. 2A below).
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With regard to claim 5, Yamazaki et al. disclose the longitudinal portions (220a, 220b) of the at least one active region (220a, 216, 220b) are laterally offset from a longitudinal portion (208b) of a different level.
With regard to claim 6, Yamazaki et al. disclose a plurality of transition regions (first and second channel regions 216B1, 216B2 function as transition regions) along a same active region (220a, 216, 220b).
With regard to claim 7, Yamazaki et al. disclose a plurality of transition regions (first and second channel regions 216B1, 216B2 function as transition regions) within active regions (216A1, 216B1, 216B2) of a same level (A2) of the at least two levels (A1, A2).
With regard to claim 8, Yamazaki et al. disclose a plurality of transition regions (first and second channel regions 216B1, 216B2 function as transition regions and regions 119A1, 119A2 as annotated in fig. 2A below) within the active regions at different levels (A1, A2) of the at least two levels (A1, A2).
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Allowable Subject Matter
3. Claims 9 - 17 are allowable over the prior art of record because none of these references disclose or can be combined to yield the claimed invention such as a transition region along at least one of the second active regions to provide an offset between at least one active region in the second level and a corresponding active region in the first level, the transition region bending the at least one active region in the second level to provide an offset space; and a vertical interconnect disposed in the offset space as recited in claim 9.
4. Claims 18 - 20 are allowable over the prior art of record because none of these references disclose or can be combined to yield the claimed invention such as a transition region along at least one of the second active regions to provide an offset between at least one active region in the second level and a corresponding active region in an adjacent level, the transition region bending the at least one active region in the second level to provide an offset space; and a vertical interconnect disposed in the offset space as recited in claim 18.
Conclusion
5. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TAN N TRAN/
Primary Examiner, Art Unit 2812
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