DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Matsudai et al. (U.S. Patent No. 10,903,346) in view of Ozaki et al. (U.S. Patent No. 12,575,149).
Regarding to claim 1, Matsudai teaches a semiconductor device, comprising:
a semiconductor substrate having a first main surface and a second main surface opposite the first main surface (Fig. 2, element 10, the first main surface in the top surface); and
an emitter wiring provided on the first main surface via an insulating film (Fig. 2, element 12, column 4, line 30),
wherein when viewed from the first main surface side, the semiconductor substrate includes:
an active region includes a plurality of IGBTs formed on the semiconductor substrate (Fig. 2, Cell Region 101; column 4, lines 22-23);
a termination region arranged to surround the active region (Fig. 2, Termination Region 103); and
a main junction region arranged between the active region and the termination region (Fig. 2, Cell End Region 102),
wherein the semiconductor substrate of the main junction region includes:
a drift layer of a first conductivity type (Fig. 2, column 4, line 9, portion of layer 32 in the Cell End Region 102); and
a junction impurity layer of a second conductivity type provided closer to the first main surface side than the drift layer (Fig. 2, column 4, line 9, portion of layer 34 in the Cell End Region 102),
wherein the semiconductor substrate in the termination region includes:
the drift layer (Fig. 2, column 4, line 9, portion of layer 32 in the Termination Region 103); and
a floating layer of the second conductivity type provided closer to the first main surface side than the drift layer (Fig. 2, element 46, column 6, lines 33-36),
wherein at least the main junction region of the semiconductor substrate includes:
a trench electrode provided inside a trench formed in the first main surface (Fig. 2, element 26); and
a trench insulating film provided between the trench electrode and the semiconductor substrate (Fig. 2, element 42),
wherein the trench electrode and the junction impurity layer are connected to the emitter wiring in the main junction region (Fig. 2).
Matsudai does not explicitly disclose when viewed from the first main surface side, the trench electrode includes a portion extending in one direction from the main junction region towards the termination region.
Ozaki discloses when viewed from the first main surface side, a trench electrode includes a portion extending in one direction from the main junction region towards the termination region (Fig, 2, Fig. 7). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Matsudai in view of Ozaki to include in the trench electrode a portion extending in one direction from the main junction region towards the termination region in order to reduce leakage.
Regarding to claim 2, Matsudai teaches when viewed from the first main surface side, both ends in the one direction of the trench electrode are located in the main junction region (Fig. 2).
Regarding to claim 6, Matsudai teaches the floating layer is not connected to the emitter wiring in the termination region (Fig, 2).
Regarding to claim 7, Matsudai teaches the emitter wiring includes: a main body portion; and an emitter contact connecting to the junction impurity layer, and wherein the junction impurity layer is connected to the emitter wiring through the emitter contact (Fig. 2).
Allowable Subject Matter
Claim 20 is allowed.
Claims 3-5 and 8-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter:
Regarding to claim 3, the prior art fails to anticipate or render obvious the claimed limitations including “when viewed from the first main surface side, the trench electrode includes a portion extending from the main junction region to the termination region, and wherein one end in the one direction of the trench electrode is located in the main junction region, and the other end is located in the termination region” in combination with the limitations recited in claim 1.
Regarding to claim 8, the prior art fails to anticipate or render obvious the claimed limitations including “wherein when viewed from the first main surface side, each of the trench electrodes and each of the trenches are annular, wherein the emitter contact includes: a first emitter contact connecting to the junction impurity layer inside the annular trench electrode; and a second emitter contact connecting to the junction impurity layer between two adjacent annular trench electrodes” in combination with the limitations recited in claims 1 and 7, and the rest of limitations recited in claim 8.
Regarding to claim 11, the prior art fails to anticipate or render obvious the claimed limitations including “wherein when viewed from the first main surface side, each of the trench electrodes and each of the trenches are annular, and wherein the emitter contact is formed across the plurality of annular trench electrodes and the junction impurity layer” in combination with the limitations recited in claims 1 and 7, and the rest of limitations recited in claim 11.
Regarding to claim 14, the prior art fails to anticipate or render obvious the claimed limitations including “a barrier layer of the first conductivity type provided closer to the first main surface side than the drift layer, an IGBT floating layer of the second conductivity type provided on the opposite side of the barrier layer, the channel layer, and the emitter layer across the gate trench electrode” in combination with the limitations recited in claim 1 and the rest of limitations recited in claim 14.
Regarding to claim 15, the prior art fails to anticipate or render obvious the claimed limitations including “the main junction region includes: a first main junction portion extending in the one direction; a second main junction portion extending in a second direction crossing the one direction; and a third main junction portion at the corner where the first and second main junction portions are connected, and wherein the trench electrode includes a portion extending in either the one direction or the second direction at the third main junction portion” in combination with the limitations recited in claim 1.
Regarding to claim 20, the prior art fails to anticipate or render obvious the claimed limitations including “a barrier layer of the first conductivity type provided closer to the first main surface side than the drift layer, an IGBT floating layer of the second conductivity type provided on the opposite side of the barrier layer, the channel layer, and the emitter layer across the gate trench electrode” in combination with the rest of limitations recited in claim 20.
Pertinent Art
For the benefits of the Applicant, US-20240258306-A1, US-7999312-B2, US-7586151-B2, US-9337298-B2, US-10714611-B2, US-10916631-B2, US-10734515-B2, and US-10714603-B2, are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. The references fail to disclose the limitations including “a barrier layer of the first conductivity type provided closer to the first main surface side than the drift layer, an IGBT floating layer of the second conductivity type provided on the opposite side of the barrier layer, the channel layer, and the emitter layer across the gate trench electrode”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VU A VU whose telephone number is (571)270-7467. The examiner can normally be reached M-F: 8:00AM - 5:00PM.
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/VU A VU/Primary Examiner, Art Unit 2897
