Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 12, 17-19, 28, 29, and 57 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ugur (US 20230023195 A1), in view of Zhang (US 20220359710 A1), and .
Regarding independent claim 1, Ugur teaches a gate-controlled semiconductor device, comprising: a semiconductor layer structure having an upper surface and a lower surface that are spaced apart from each other in a depth direction (Fig. 8, 320; [0174], "The MOSFET 300 of FIG. 8 includes gate fingers 334 that are formed in trenches 321 within the semiconductor layer structure 320…"); and a gate trench in the semiconductor layer structure (Fig. 8, 321; [0174], "The MOSFET 300 of FIG. 8 includes gate fingers 334 that are formed in trenches 321 within the semiconductor layer structure 320…"); wherein the semiconductor layer structure comprises: a drift region that has a first conductivity type (Fig. 8, 124; [0147], "The semiconductor layer structure further includes a lightly-doped n-type (n^−) silicon carbide drift region 124 is provided on an upper surface of the substrate…"); and a trench shield that has a second conductivity type, the trench shield underneath the gate trench (Fig. 8, 329; [0174], "Additionally, p-type shielding regions 329 may be formed beneath all or part of each trench 321…").
However, Ugur does not teach and a support shield that has the second conductivity type extending toward the lower surface of the semiconductor layer structure, wherein the support shield has a peak doping concentration at a first depth from the upper surface of the semiconductor layer structure, wherein a lowermost portion of the trench shield is at a second depth from the upper surface of the semiconductor layer structure that is less than the first depth, and wherein the thickness of the trench shield in the depth direction is less than the first depth minus the second depth.
However, in the same field of endeavor, Zhang teaches a support shield that has the second conductivity type extending toward the lower surface of the semiconductor layer structure (Fig. 5, 380; [0085], "...there is a p-doped pillar 380 that extends downward from the shield 370 through at least a portion of the drift region 350. "), wherein the support shield has a peak doping concentration at a first depth from the upper surface of the semiconductor layer structure ([0087], "The concentration of the p-doped region is nearly uniform…", (If the concentration is uniform, it can be said that it has a "peak" at all depths)), wherein a lowermost portion of the trench shield is at a second depth from the upper surface of the semiconductor layer structure that is less than the first depth (Fig. 5, 370; [0085], "...there is a p-doped pillar 380 that extends downward from the shield 370 through at least a portion of the drift region 350. "), and wherein the thickness of the trench shield in the depth direction is less than the first depth minus the second depth ([0085], "This thickness of this p-doped pillar 380 may be 10 μm or more.", [0063], "...the trench 330 may have a depth that is equal to or greater than 1.5 μm.", [0068], "...the shield 370 may extend to a depth that is at least equal to the depth of the trench 330.").
Therefore, it would be obvious to one of ordinary skill in the art to combine the gate-controlled semiconductor device of Ugur with the support shields of Zhang so as to "allow higher doping concentration of the drift region", (Zhang, [0085]).
Regarding dependent claim 2, Ugur, as previously modified by Zhang, teaches the gate-controlled semiconductor device of claim 1. However, as previously combined, they do not teach wherein the trench shield has a peak doping concentration at a third depth from the upper surface of the semiconductor layer structure, and wherein a thickness of the trench shield in the depth direction is less than the first depth minus the third depth.
However, Zhang further teaches wherein the trench shield has a peak doping concentration at a third depth from the upper surface of the semiconductor layer structure ([0078], "...to achieve a nearly uniformly doped shield 370.", (Once again, with a uniform concentration, the "peak" can be said to be at any depth)), and wherein a thickness of the trench shield in the depth direction is less than the first depth minus the third depth ([0085], "This thickness of this p-doped pillar 380 may be 10 μm or more.", [0063], "...the trench 330 may have a depth that is equal to or greater than 1.5 μm.", [0068], "...the shield 370 may extend to a depth that is at least equal to the depth of the trench 330.").
Therefore, it would have been obvious to one of ordinary skill in the art to combine the gate-controlled semiconductor device as described by the combination of Ugur and Zhang with the doping concentration of Zhang so as to "allow a reduction in the number of epitaxially growth processes", (Zhang, [0006]).
Regarding dependent claim 12, Ugur, as previously modified by Zhang, teaches the gate-controlled semiconductor device of claim 1. Zhang further teaches wherein a lowermost portion of the support shield is at a fifth depth from the upper surface of the semiconductor layer structure that is more than three times greater than a minimum lateral distance between a sidewall of the trench shield and a facing sidewall of the support shield (Fig. 5, Since the support shields are directly adjacent to the trench shields, they are necessarily at a depth of more than three times the distance to the trenches.).
Regarding independent claim 17, Ugur teaches a gate-controlled semiconductor device, comprising: a semiconductor layer structure having an upper surface and a lower surface that are spaced apart from each other in a depth direction (Fig. 8, 320; [0174], "The MOSFET 300 of FIG. 8 includes gate fingers 334 that are formed in trenches 321 within the semiconductor layer structure 320…"); and a gate trench in the semiconductor layer structure (Fig. 8, 321; [0174], "The MOSFET 300 of FIG. 8 includes gate fingers 334 that are formed in trenches 321 within the semiconductor layer structure 320…"); wherein the semiconductor layer structure comprises: a drift region that has a first conductivity type (Fig. 8, 124; [0147], "The semiconductor layer structure further includes a lightly-doped n-type (n^−) silicon carbide drift region 124 is provided on an upper surface of the substrate…"); a trench shield that has a second conductivity type, the trench shield underneath the gate trench (Fig. 8, 329; [0174], "Additionally, p-type shielding regions 329 may be formed beneath all or part of each trench 321…").
However, Ugur does not teach and a support shield that has the second conductivity type extending toward the lower surface of the semiconductor layer structure, the support shield adjacent the trench shield, wherein the lower surface of the semiconductor layer structure and a segment extending between a point on a sidewall of the support shield that is at a first depth from the upper surface of the semiconductor layer structure where the support shield has a peak doping concentration and a point on a facing sidewall of the trench shield that is at a third depth from the upper surface of the semiconductor layer structure where the trench shield has a peak doping concentration defines an angle of at least 30°.
However, Zhang teaches a support shield that has the second conductivity type extending toward the lower surface of the semiconductor layer structure, the support shield adjacent the trench shield (Fig. 5, 380; [0085], "...there is a p-doped pillar 380 that extends downward from the shield 370 through at least a portion of the drift region 350. "), wherein the lower surface of the semiconductor layer structure and a segment extending between a point on a sidewall of the support shield that is at a first depth from the upper surface of the semiconductor layer structure where the support shield has a peak doping concentration and a point on a facing sidewall of the trench shield that is at a third depth from the upper surface of the semiconductor layer structure where the trench shield has a peak doping concentration defines an angle of at least 30° (Fig. 5; [0087], "The concentration of the p-doped region is nearly uniform…", (If the concentration is uniform, it can be said that it has a "peak" at all depths), [0078], "...to achieve a nearly uniformly doped shield 370.", (Once again, with a uniform concentration, the "peak" can be said to be at any depth), (Since each has uniform concentration, a line of nearly any angle can be drawn from the "peak position" of the trench shield to the same of the support shield)).
Therefore, it would be obvious to one of ordinary skill in the art to combine the gate-controlled semiconductor device of Ugur with the support shields of Zhang so as to "allow higher doping concentration of the drift region", (Zhang, [0085]).
Regarding dependent claim 18, Ugur, as previously modified by Zhang teaches the gate-controlled semiconductor device of Claim 17. However, as previously combined, they do not teach wherein a lowermost portion of the trench shield is at a second depth from the upper surface of the semiconductor layer structure that is less than the first depth, and wherein a thickness of the trench shield in the depth direction is less than the first depth minus the second depth.
However, Zhang further teaches wherein a lowermost portion of the trench shield is at a second depth from the upper surface of the semiconductor layer structure that is less than the first depth (Fig. 5, 370; [0085], "...there is a p-doped pillar 380 that extends downward from the shield 370 through at least a portion of the drift region 350. "), and wherein a thickness of the trench shield in the depth direction is less than the first depth minus the second depth ([0085], "This thickness of this p-doped pillar 380 may be 10 μm or more.", [0063], "...the trench 330 may have a depth that is equal to or greater than 1.5 μm.", [0068], "...the shield 370 may extend to a depth that is at least equal to the depth of the trench 330.").
Therefore, it would have been obvious to one of ordinary skill in the art to combine the gate-controlled semiconductor device as described by the combination of Ugur, Zhang, and with the depth and thickness of the trench shield of Zhang so as to "allow a reduction in the number of epitaxially growth processes", (Zhang, [0006]).
Regarding dependent claim 19, Ugur, as previously modified by Zhang teaches the gate-controlled semiconductor device of claim 17. However, as previously combined, they do not teach wherein a thickness of the trench shield in the depth direction is less than the first depth minus the third depth.
However, Zhang further teaches wherein a thickness of the trench shield in the depth direction is less than the first depth minus the third depth ([0085], "This thickness of this p-doped pillar 380 may be 10 μm or more.", [0063], "...the trench 330 may have a depth that is equal to or greater than 1.5 μm.", [0068], "...the shield 370 may extend to a depth that is at least equal to the depth of the trench 330.").
Therefore, it would have been obvious to one of ordinary skill in the art to combine the gate-controlled semiconductor device as described by the combination of Ugur, Zhang, and with the thickness of the trench shield of Zhang so as to “allow a reduction in the number of epitaxially growth processes", (Zhang, [0006]).
Regarding dependent claim 28, Ugur, as previously modified by Zhang teaches the gate-controlled semiconductor device of Claim 17. Zhang further teaches wherein a maximum depth of the support shield into the semiconductor layer structure is more than three times greater than a minimum lateral distance between a sidewall of the trench shield and a facing sidewall of the support shield (Fig. 5, Since the support shields are directly adjacent to the trench shields, they are necessarily at a depth of more than three times the distance to the trenches.).
Regarding dependent claim 29, Ugur, as previously modified by Zhang teaches the gate-controlled semiconductor device of claim 17. Ugur further teaches wherein the semiconductor layer structure further comprises a well region that has the second conductivity type on the drift region (Fig. 8, 126; [0148], "P-type well regions 126 are formed in upper portions of the n-type drift region 124…"), the well region comprising a channel region adjacent the gate trench (Fig. 3C, 127; [0148], "Channel regions 127 are defined in the sides of the well regions 126."), and Zhang further teaches and wherein a difference between a maximum depth of the support shield from the upper surface of the semiconductor layer structure and a maximum depth of the channel region from the upper surface of the semiconductor layer structure is more than five times a thickness of the trench shield in the depth direction ([0085], "This thickness of this p-doped pillar 380 may be 10 μm or more.", [0063], "...the trench 330 may have a depth that is equal to or greater than 1.5 μm.", [0068], "...the shield 370 may extend to a depth that is at least equal to the depth of the trench 330.").
Regarding independent claim 57, Ugur teaches a gate-controlled semiconductor device, comprising: a semiconductor layer structure having an upper surface and a lower surface that are spaced apart from each other in a depth direction (Fig. 8, 320; [0174], "The MOSFET 300 of FIG. 8 includes gate fingers 334 that are formed in trenches 321 within the semiconductor layer structure 320…"); and a gate trench in the semiconductor layer structure (Fig. 8, 321; [0174], "The MOSFET 300 of FIG. 8 includes gate fingers 334 that are formed in trenches 321 within the semiconductor layer structure 320…"); wherein the semiconductor layer structure comprises: a drift region that has a first conductivity type (Fig. 8, 124; [0147], "The semiconductor layer structure further includes a lightly-doped n-type (n^−) silicon carbide drift region 124 is provided on an upper surface of the substrate…"); and a trench shield that has a second conductivity type, the trench shield underneath the gate trench (Fig. 8, 329; [0174], "Additionally, p-type shielding regions 329 may be formed beneath all or part of each trench 321…").
However, Ugur does not teach and a support shield that has the second conductivity type extending toward the lower surface of the semiconductor layer structure, the support shield adjacent the trench shield, wherein the lower surface of the semiconductor layer structure and a segment extending between a point on a sidewall of the support shield that is closest in the lateral direction to the trench shield and a point on a facing sidewall of the trench shield that is at a third depth from the upper surface of the semiconductor layer structure where the trench shield has a peak doping concentration defines an angle of at least 20°.
However, in the same field of endeavor, Zhang teaches a support shield that has the second conductivity type extending toward the lower surface of the semiconductor layer structure, the support shield adjacent the trench shield (Fig. 5, 380; [0085], "...there is a p-doped pillar 380 that extends downward from the shield 370 through at least a portion of the drift region 350. "), wherein the lower surface of the semiconductor layer structure and a segment extending between a point on a sidewall of the support shield that is closest in the lateral direction to the trench shield and a point on a facing sidewall of the trench shield that is at a third depth from the upper surface of the semiconductor layer structure where the trench shield has a peak doping concentration defines an angle of at least 20° (Fig. 5; [0087], "The concentration of the p-doped region is nearly uniform…", (If the concentration is uniform, it can be said that it has a "peak" at all depths), [0078], "...to achieve a nearly uniformly doped shield 370.", (Once again, with a uniform concentration, the "peak" can be said to be at any depth), (Since each has uniform concentration, a line of nearly any angle can be drawn from the "peak position" of the trench shield to the same of the support shield)).
Therefore, it would be obvious to one of ordinary skill in the art to combine the gate-controlled semiconductor device of Ugur with the support shields of Zhang so as to "allow higher doping concentration of the drift region", (Zhang, [0085]).
Claim(s) 3 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ugur (US 20230023195 A1), in view of Zhang (US 20220359710 A1), and Islam (US 20220173227 A1).
Regarding dependent claim 3, Ugur, as previously modified by Zhang, teaches the gate-controlled semiconductor device of claim 1. However, as previously combined, they do not teach wherein a peak doping concentration of the trench shield and the peak doping concentration of the support shield differ by no more than a factor of three.
However, in the same field of endeavor, Islam teaches wherein a peak doping concentration of the trench shield and the peak doping concentration of the support shield differ by no more than a factor of three (Fig. 10, 1040, 1040c; [0114], "The central shielding region 940c, 1040c, 1140 may be a buried region at or below a base of the fin structure 275, and may be formed, for example, by ion implantation and with a dopant concentration similar to the peripherally-located shielding regions (e.g., 940, 1040).", (Since the concentrations are the same, they do not differ by more than a factor of three)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the gate-controlled semiconductor device as described by the combination of Ugur and Zhang with the difference in doping concentration as described by Islam so as to "allow process flexibility", (Islam, [0072]).
Regarding dependent claim 20, Ugur, as previously modified by Zhang teaches the gate-controlled semiconductor device of Claim 17. However, as previously combined, they do not teach wherein the peak doping concentration of the trench shield and the peak doping concentration of the support shield differ by no more than a factor of three.
However, in the same field of endeavor, Islam teaches wherein the peak doping concentration of the trench shield and the peak doping concentration of the support shield differ by no more than a factor of three (Fig. 10, 1040, 1040c; [0114], "The central shielding region 940c, 1040c, 1140 may be a buried region at or below a base of the fin structure 275, and may be formed, for example, by ion implantation and with a dopant concentration similar to the peripherally-located shielding regions (e.g., 940, 1040).", (Since the concentrations are the same, they do not differ by more than a factor of three)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the gate-controlled semiconductor device as described by the combination of Ugur and Zhang with the difference in doping concentration as described by Islam so as to "allow process flexibility", (Islam, [0072]).
Claim(s) 6, 8, 23, 24, and 61-63 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ugur (US 20230023195 A1), in view of Zhang (US 20220359710 A1), Islam (US 20220173227 A1), and Salemi (US 20220262902 A1).
Regarding dependent claim 6, Ugur, as previously combined with Zhang, teaches the gate-controlled semiconductor device of Claim 1. However, as previously combined, they do not teach wherein an upper portion of the drift region comprises a JFET region that has the first conductivity type and a peak doping concentration that is at least an order of magnitude greater than a peak doping concentration of a lower portion of the drift region, and a peak doping concentration of the trench shield is less than two orders of magnitude greater than the peak doping of the concentration of the JFET region.
However, in the same field of endeavor, Salemi teaches wherein an upper portion of the drift region comprises a JFET region that has the first conductivity type and a peak doping concentration that is at least an order of magnitude greater than a peak doping concentration of a lower portion of the drift region (Fig. 8F, 803; [0045], "The JFET region may be doped by implanting ions of the first conductivity type at a greater concentration that the epitaxial layer 802."), and Islam teaches and a peak doping concentration of the trench shield is less than two orders of magnitude greater than the peak doping of the concentration of the JFET region ([0087], "For example, the shielding regions described herein may be formed by implanting a p-type dopant with a concentration of between about 1×10^15 atoms/cm^3 and 1×10^20 atoms/cm^3…", [0099], " For example, the JFET region 530 may be doped with n-type impurities, and may have a dopant concentration of about 1×10^15 to 1×10^20 atoms/cm^3, or about 1×10^16 to 2×10^18 atoms/cm^3.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the gate-controlled semiconductor device as described by the combination of Ugur and Zhang with the JFET region of Salemi so as to "allow current to flow through the device", (Salemi, [0003]), and with the concentration of Islam so as to "reduce the parasitic resistance in the JFET region", (Islam, [0099]).
Regarding dependent claim 8, Ugur, as previously modified by Zhang, Salemi, and Islam, teaches the gate-controlled semiconductor device of Claim 6. However, as previously combined, they do not teach wherein a lowermost portion of the JFET region is at a fourth depth from the upper surface of the semiconductor layer structure that is deeper than the second depth, and a lowermost portion of the support shield is at a fifth depth from the upper surface of the semiconductor layer structure that is deeper than the fourth depth.
However, Salemi further teaches wherein a lowermost portion of the JFET region is at a fourth depth from the upper surface of the semiconductor layer structure that is deeper than the second depth (Fig. 8D, 803, 807, (The JFET extends lower than the trench 807)), and Islam teaches and a lowermost portion of the support shield is at a fifth depth from the upper surface of the semiconductor layer structure that is deeper than the fourth depth (Fig. 7, 630, 74-; [0106], "The deeper shielding regions 740 shown in FIG. 7 may more effectively protect the gate insulating layer 282 from premature breakdown, while also maintaining the gap g′ in the JFET region 630 to reduce the parasitic resistance.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the gate-controlled semiconductor device as described by the combination of Ugur, Zhang, Salemi, and Islam with the depth of Salemi so as to make a "semiconductor device with improved cell geometry", (Salemi, [0044]), and the depth of Islam so as to "reduce parastic resistance", (Islam, [0106]).
Regarding dependent claim 23, Ugur, as previously modified by Zhang teaches the gate-controlled semiconductor device of Claim 18. However, as previously combined, they do not teach wherein an upper portion of the drift region comprises a JFET region that has the first conductivity type and a peak doping concentration that is at least an order of magnitude greater than a peak doping concentration of a lower portion of the drift region.
However, in the same field of endeavor, Salemi teaches wherein an upper portion of the drift region comprises a JFET region that has the first conductivity type and a peak doping concentration that is at least an order of magnitude greater than a peak doping concentration of a lower portion of the drift region (Fig. 8F, 803; [0045], "The JFET region may be doped by implanting ions of the first conductivity type at a greater concentration that the epitaxial layer 802.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the gate-controlled semiconductor device as described by the combination of Ugur and Zhang with the JFET region of Salemi so as to "allow current to flow through the device", (Salemi, [0003]).
Regarding dependent claim 24, Ugur, as previously modified by Zhang and Salemi, teaches the gate-controlled semiconductor device of Claim 23. However, as previously combined, they do not teach wherein a peak doping concentration of the trench shield is less than two orders of magnitude greater than the peak doping of the concentration of the JFET region.
However, in the same field of endeavor, Islam teaches wherein a peak doping concentration of the trench shield is less than two orders of magnitude greater than the peak doping of the concentration of the JFET region ([0087], "For example, the shielding regions described herein may be formed by implanting a p-type dopant with a concentration of between about 1×10^15 atoms/cm^3 and 1×10^20 atoms/cm^3…", [0099], " For example, the JFET region 530 may be doped with n-type impurities, and may have a dopant concentration of about 1×10^15 to 1×10^20 atoms/cm^3, or about 1×10^16 to 2×10^18 atoms/cm^3.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the gate-controlled semiconductor device as described by the combination of Ugur, Zhang, and Salemi with the concentration of Islam so as to "reduce the parasitic resistance in the JFET region", (Islam, [0099]).
Regarding dependent claim 61, Ugur, as previously modified by Zhang, teaches the gate-controlled semiconductor device of Claim 57. However, as previously combined, they do not teach wherein an upper portion of the drift region comprises a JFET region that has the first conductivity type and a peak doping concentration that is at least an order of magnitude greater than a peak doping concentration of a lower portion of the drift region.
However, in the same field of endeavor, Salemi teaches wherein an upper portion of the drift region comprises a JFET region that has the first conductivity type and a peak doping concentration that is at least an order of magnitude greater than a peak doping concentration of a lower portion of the drift region (Fig. 8F, 803; [0045], "The JFET region may be doped by implanting ions of the first conductivity type at a greater concentration that the epitaxial layer 802.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the gate-controlled semiconductor device as described by the combination of Ugur and Zhang with the JFET region of Salemi so as to "allow current to flow through the device", (Salemi, [0003]).
Regarding dependent claim 62, Ugur, as previously modified by Zhang and Salemi, teaches the gate-controlled semiconductor device of Claim 62. However, as previously combined, they do not teach wherein a lowermost portion of the JFET region is at a fourth depth from the upper surface of the semiconductor layer structure that is deeper than a second depth that corresponds to a lowermost portion of the trench shield from the upper surface of the semiconductor layer structure.
However, Salemi further teaches wherein a lowermost portion of the JFET region is at a fourth depth from the upper surface of the semiconductor layer structure that is deeper than a second depth that corresponds to a lowermost portion of the trench shield from the upper surface of the semiconductor layer structure (Fig. 8D, 803, 807, (The JFET extends lower than the trench 807)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the gate-controlled semiconductor device as described by the combination of Ugur, Zhang, and Salemi with the depth of the JFET region of Salemi so as to make a "semiconductor device with improved cell geometry", (Salemi, [0044]).
Regarding dependent claim 63, Ugur, as previously modified by Zhang, and Salemi, teaches the gate-controlled semiconductor device of Claim 62. However, as previously combined, they do not teach wherein a lowermost portion of the support shield is at a fifth depth from the upper surface of the semiconductor layer structure that is deeper than the fourth depth.
However, in the same field of endeavor, Islam teaches wherein a lowermost portion of the support shield is at a fifth depth from the upper surface of the semiconductor layer structure that is deeper than the fourth depth (Fig. 7, 630, 74-; [0106], "The deeper shielding regions 740 shown in FIG. 7 may more effectively protect the gate insulating layer 282 from premature breakdown, while also maintaining the gap g′ in the JFET region 630 to reduce the parasitic resistance.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the gate-controlled semiconductor device as described by the combination of Ugur, Zhang, and Salemi with the depth of the shield of Islam so as to "reduce parastic resistance", (Islam, [0106]).
Claim(s) 59 and 60 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ugur (US 20230023195 A1), in view of Zhang (US 20220359710 A1), and Yilmaz (US 20230100800 A1).
Regarding dependent claim 59, Ugur, as previously modified by Zhang, teaches the gate-controlled semiconductor device of Claim 57. However, as previously combined, they do not teach wherein a thickness of the trench shield is less than 0.3 microns.
However, in the same field of endeavor, Yilmaz teaches wherein a thickness of the trench shield is less than 0.3 microns (Fig. 1A, 18; [0043], "Polysilicon shield regions 18 may initially be deposited to a thickness in a range between 0.25 and 1.0 micron…").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the gate-controlled semiconductor device as described by the combination of Ugur and Zhang with the shield thickness of Yilmaz so as to "to resolve reliability and fabrication challenges of the thick shielded gate structures", (Yilmaz, [0023]).
Regarding dependent claim 60, Ugur, as previously modified by Zhang, teaches the gate-controlled semiconductor device of Claim 57. However, as previously combined, they do not teach wherein the peak doping concentration of the trench shield is at a depth of between 0.6 and 1.1 microns from the upper surface of the semiconductor layer structure.
However, in the same field of endeavor, Yilmaz teaches wherein the peak doping concentration of the trench shield is at a depth of between 0.6 and 1.1 microns from the upper surface of the semiconductor layer structure (Fig. 1A, 18; [0043], "Polysilicon shield regions 18 may initially be deposited to a thickness in a range between 0.25 and 1.0 micron…", "A boron implant dose to the P polysilicon 18 may be in the range from about 5e12 to 1e15 cm^-2…" (Since only one value is given for the concentration, it can be assumed to be constant, and the range of the thickness is within the range given in the present application)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the gate-controlled semiconductor device as described by the combination of Ugur and Zhang with the trench shield depth of Yilmaz so as to "to resolve reliability and fabrication challenges of the thick shielded gate structures", (Yilmaz, [0023]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20210320178 A1, pertaining to a semiconductor device with a trench and a shield on said trench.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOTHY JAMES MATTABONI whose telephone number is (571)270-0766. The examiner can normally be reached Monday-Friday 9 AM - 5 PM.
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/TIMOTHY JAMES MATTABONI/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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