Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai (US 10074558 B1), in view of Liu (US 6150272 A).
Regarding independent claim 1, Tsai teaches a semiconductor structure, comprising: a first ILD layer disposed over a substrate (Fig. 7E, 235; Col. 6, Lines 27-28, "...in which an inter-level dielectric material (ILD) 235 is formed on the substrate…"); and a first barrier layer disposed in the first ILD layer (Col. 7, Lines 54-56, "...a barrier layer may be formed on deposited for lining the gate trenches before filling the metal.").
However, Tsai does not teach a patterned metal structure disposed in the first ILD layer the patterned metal structure including a metal plug and a first metal layer having a first metal line; wherein the first metal line contacts the first barrier layer and is separated from the first ILD layer by the first barrier layer, and the metal plug contacts the first ILD layer.
However, in the same field of endeavor, Liu teaches a patterned metal structure disposed in the first ILD layer (Fig. 9, 12; Col. 3, Lines 59-63, "... a patterned conducting layer 12, such as a doped polysilicon, polycide layer, or metal layer is formed on the substrate surface to form portions of the devices and/or local interconnections."), the patterned metal structure including a metal plug and a first metal layer having a first metal line (Fig. 9, 22, 34; Col. 5, Lines, 8-10, "...the metal plugs 22, which are essentially planar with the surface of the insulating layer 14, are now completed…", Col. 6, Lines 4-6, "...the interconnecting metal lines 34, which are essentially planar with the surface of the second insulating layer 26, are now completed..."); wherein the first metal line contacts the first barrier layer and is separated from the first ILD layer by the first barrier layer (Fig. 9, 32; Col. 5, Lines 62-64, "...the metal layer 34 and the barrier/adhesion layer 32 are then chemically/mechanically polished…"), and the metal plug contacts the first ILD layer (Fig. 9, 22, 14; Col. 4, Lines 4-5, "Preferably the insulating layer 14 is a low-dielectric oxide-based insulator.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor structure of Tsai with the patterned metal structure of Tsai "for interconnecting discrete semiconductor devices on a substrate", (Liu, Col. 2, Lines 14-15).
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai (US 10074558 B1), in view of Liu (US 6150272 A) and Watanabe (US 20170025354 A1).
Regarding dependent claim 2, Tsai, as previously modified by Liu, teaches the semiconductor structure of claim 1. However, as previously combined, they do not teach wherein the patterned metal structure having a continuous sidewall slope from the metal plug to the first metal line.
However, in the same field of endeavor, Watanabe teaches wherein the patterned metal structure having a continuous sidewall slope from the metal plug to the first metal line (Fig. 10, 121b, 611; [0074], "...to connect bit line 121b with contact plug 611.", (In the diagram, the sidewall is sloped and continuous between the two)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor structure as described by the combination of Tsai and Liu with the continuous sidewall slope of Watanabe so as "to connect the memory array and various peripheral circuits", (Watanabe, [0005]).
Claim(s) 10-14, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai (US 10074558 B1), in view of Liu (US 6150272 A), Watanabe (US 20170025354 A1), and Zhang (US 20160111368 A1).
Regarding independent claim 10, Tsai teaches a semiconductor structure, comprising: a semiconductor substrate; and a first ILD layer disposed over the semiconductor substrate (Fig. 7E, 235; Col. 6, Lines 27-28, "...in which an inter-level dielectric material (ILD) 235 is formed on the substrate…").
However, Tsai does not teach and a patterned metal structure disposed in the first ILD layer, the patterned metal structure including a metal plug and a first metal feature, the patterned metal structure having a continuous sidewall slope from the metal plug to the first metal feature.
However, in the same field of endeavor, Liu teaches a patterned metal structure disposed in the first ILD layer (Fig. 9, 12; Col. 3, Lines 59-63, "... a patterned conducting layer 12, such as a doped polysilicon, polycide layer, or metal layer is formed on the substrate surface to form portions of the devices and/or local interconnections."), the patterned metal structure including a metal plug and a first metal feature (Fig. 9, 22, 34; Col. 5, Lines, 8-10, "...the metal plugs 22, which are essentially planar with the surface of the insulating layer 14, are now completed…", Col. 6, Lines 4-6, "...the interconnecting metal lines 34, which are essentially planar with the surface of the second insulating layer 26, are now completed..."), and Watanabe teaches the patterned metal structure having a continuous sidewall slope from the metal plug to the first metal feature (Fig. 10, 121b, 611; [0074], "...to connect bit line 121b with contact plug 611.", (In the diagram, the sidewall is sloped and continuous between the two)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor structure of Tsai with the patterned metal structure of Liu "for interconnecting discrete semiconductor devices on a substrate", (Liu, Col. 2, Lines 14-15), and the continuous sidewall of Watanabe so as "to connect the memory array and various peripheral circuits", (Watanabe, [0005]).
Regarding dependent claim 11, Tsai, as previously modified by Liu and Watanabe, teaches the semiconductor structure of claim 10. However, as previously combined, they do not teach wherein the patterned metal structure narrows in width from top to bottom.
However, in the same field of endeavor, Zhang teaches wherein the patterned metal structure narrows in width from top to bottom (Fig. 10, 209; [0085], " Accordingly, the shape of the cross-section of the second metal layers 209 formed to fill up the openings also has a wider upper edge and narrower lower edge.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor structure as described by the combination of Tsai, Liu, and Watanabe with the narrowing width of Zhang so as to "meet with the development trend of miniaturization of semiconductor technology", (Zhang, [0005]).
Regarding dependent claim 12, Tsai, as previously modified by Liu, Watanabe, and Zhang, teaches the semiconductor structure of claim 11, and further teaches further comprising a first barrier layer directly disposed on bottom and sidewall surfaces of the patterned metal structure (Col. 7, Lines 54-56, "...a barrier layer may be formed on deposited for lining the gate trenches before filling the metal.").
Regarding dependent claim 13, Tsai, as previously modified by Liu, Watanabe, and Zhang, teaches the semiconductor structure of claim 12, and further teaches further comprising a first etch stop layer (ESL) underlying a bottom surface of the first ILD layer (Col. 6, Lines 41-43, "In an alternative embodiment, an etch stop layer may deposited on the substrate before the forming of the ILD 235…"), wherein the first barrier layer laterally contacts the first ESL (Fig. 7E, Although neither layer is shown on the diagram, the specification states that the ESL is directly below the substrate 235 and that the barrier layer is directly below the metal plugs 260. This would mean that the two contact each other.).
Regarding dependent claim 14, Tsai, as previously modified by Liu, Watanabe, and Zhang, teaches the semiconductor structure of claim 13, and further teaches wherein a bottom surface of the first barrier layer laterally and a bottom surface of the first ESL are coplanar (Fig. 7E, Although neither layer is shown on the diagram, the specification states that the ESL is directly below the substrate 235 and that the barrier layer is directly below the metal plugs 260. This would mean that the two contact each other, and be coplanar.).
Regarding independent claim 17, Tsai teaches a semiconductor structure, comprising: a first ILD layer disposed over a substrate (Fig. 7E, 235; Col. 6, Lines 27-28, "...in which an inter-level dielectric material (ILD) 235 is formed on the substrate…").
However, Tsai does not teach and a patterned metal structure disposed in the first ILD layer, the patterned metal structure including a metal plug and a first metal layer having first metal lines, the patterned metal structure having a continuous sidewall slope from the metal plug to a first one of the first metal lines, and wherein the patterned metal structure expands in width from top to bottom.
However, in the same field of endeavor, Liu teaches a patterned metal structure disposed in the first ILD layer (Fig. 9, 12; Col. 3, Lines 59-63, "... a patterned conducting layer 12, such as a doped polysilicon, polycide layer, or metal layer is formed on the substrate surface to form portions of the devices and/or local interconnections."), the patterned metal structure including a metal plug and a first metal layer having first metal lines (Fig. 9, 22, 34; Col. 5, Lines, 8-10, "...the metal plugs 22, which are essentially planar with the surface of the insulating layer 14, are now completed…", Col. 6, Lines 4-6, "...the interconnecting metal lines 34, which are essentially planar with the surface of the second insulating layer 26, are now completed..."), Watanabe teaches the patterned metal structure having a continuous sidewall slope from the metal plug to a first one of the first metal lines (Fig. 10, 121b, 611; [0074], "...to connect bit line 121b with contact plug 611.", (In the diagram, the sidewall is sloped and continuous between the two)), and Zhang teaches and wherein the patterned metal structure expands in width from top to bottom (Fig. 10, 203; [0050], "Accordingly, after forming the openings 206, the shape of the cross-section of the simultaneously formed first metal layers 203 has a narrower upper edge and a wider lower edge.").
Therefore, it would have been obvious to one of ordinary skill in the art to combine the semiconductor structure of Tsai with the patterned metal structure of Liu "for interconnecting discrete semiconductor devices on a substrate", (Liu, Col. 2, Lines 14-15), the continuous sidewall slope of Watanabe so as "to connect the memory array and various peripheral circuits", (Watanabe, [0005]), and the expansion in width of Zhang so as to "meet with the development trend of miniaturization of semiconductor technology", (Zhang, [0005]).
Claim(s) 3, 4, and 6-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai (US 10074558 B1), in view of Liu (US 6150272 A) and Kim (US 20100119700 A1).
Regarding dependent claim 3, Tsai, as previously modified by Liu, teaches the semiconductor structure of claim 1, and further teaches further comprising: a second ILD layer disposed over the first ILD layer (Fig. 7E, 245; Col. 8, Lines 11-12, "...an operation 118 to form a second ILD layer 245…"). However, as previously combined, they do not teach and a second metal layer disposed in the second ILD layer and including a third and fourth metal lines, the third metal line directly contacting a top surface of the metal plug.
However, in the same field of endeavor, Kim teaches a second metal layer disposed in the second ILD layer and including a third and fourth metal lines (Fig. 8, 160, 140; [0043], "Next, a second metal line 160 is formed in the via hole 141…", [0036], "Then, as shown in FIG. 6, a second interlayer dielectric layer 140 is deposited…"), the third metal line directly contacting a top surface of the metal plug (Fig. 2, 120, Fig. 8, 160, (Although first metal line 120 is not labeled in Fig. 8, it is evidently still there and the second metal line 160 is on top of it)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the semiconductor structure as described by the combination of Tsai and Liu with the additional layers of Kim so as to improve the distance between components (Kim, [0008]).
Regarding dependent claim 4, Tsai, as previously modified by Liu and Kim, teaches the semiconductor structure of claim 3, and further teaches a first etch stop layer (ESL) disposed underlying the first ILD layer (Col. 6, Lines 41-43, "In an alternative embodiment, an etch stop layer may deposited on the substrate before the forming of the ILD 235…").
However, as previously combined, they do not teach further comprising a second barrier layer disposed in the second ILD layer; and a second ESL disposed overlying the first ILD layer, wherein a portion of the second barrier is interposed between the third metal line and the second ESL.
However, Kim further teaches further comprising a second barrier layer disposed in the second ILD layer (Fig. 8, 150; [0041], "Thereafter, referring to FIG. 8, a second barrier layer 150 is formed in the via hole 141 and the trench 142."); and a second ESL disposed overlying the first ILD layer (Fig. 8, 170; [0044], "...are performed to form a second etch stop layer 170 as shown in FIG. 8."), wherein a portion of the second barrier is interposed between the third metal line and the second ESL (Fig. 8, 170, 150, 140 (The ESL layer is between the barrier layer and the ILD layer)).
Therefore, it would have been obvious to combine the semiconductor structure as described by the combination of Tsai, Liu, and Kim with the additional layers of Kim for "connecting the metal lines", (Kim, [0007]).
Regarding dependent claim 6, Tsai, as previously modified by Liu and Kim, teaches the semiconductor structure of claim 4. Kim further teaches wherein the fourth metal line include a bottom surface disposed on a top surface of the second barrier layer (Fig. 2, 120, Fig. 8, 160, (Although first metal line 120 is not labeled in Fig. 8, it is evidently still there and the second metal line 160 is on top of it)).
Regarding dependent claim 7, Tsai, as previously modified by Liu and Kim, teaches the semiconductor structure of claim 4. Kim further teaches wherein the second barrier layer wraps around sidewalls of the fourth metal line (Fig. 8, 150, 160, (It is evident that the barrier 150 wraps around the metal line 160)).
Regarding dependent claim 8, Tsai, as previously modified by Liu and Kim, teaches the semiconductor structure of claim 4. Kim further teaches wherein the fourth metal line is separated from the first ILD layer by the second barrier layer and the second ESL layer; and the fourth metal line is separated from the second ILD layer by the ESL layer (Fig. 8, 170, 150, 140 (The ESL layer is between the barrier layer and the ILD layer)).
Claim(s) 5 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai (US 10074558 B1), in view of Liu (US 6150272 A), Kim (US 20100119700 A1), and Watanabe (US 20170025354 A1).
Regarding dependent claim 5, Tsai, as previously modified by Liu and Kim, teaches the semiconductor structure of claim 4. However, as previously combined, they do not teach wherein the third metal line vertically extends below a bottom surface of the second barrier layer.
However, in the same field of endeavor, Watanabe teaches wherein the third metal line vertically extends below a bottom surface of the second barrier layer (Fig. 10, 121a, 121b, Fig. 9, 615; [0074], "FIG. 10 shows the result of depositing barrier layer metal (e.g. titanium, Ti, or titanium nitride, TiN) and bit line metal (e.g. copper, Cu) to fill trenches 615a-b…", " Bit lines 121a-b are thus formed in the trenches 615a-b...", (One metal line is below the other)).
Therefore, it would have been obvious to combine the semiconductor structure as described by the combination of Tsai, Liu, and Kim with the extension of the metal line of Watanabe so as to "maintain a minimum distance from neighboring contact plugs", (Watanabe, [0075]).
Regarding dependent claim 9, Tsai, as previously modified by Liu and Kim, teaches the semiconductor structure of claim 4. However, as previously combined, they do not teach wherein the third metal line and the fourth metal line vertically extend different heights.
However, in the same field of endeavor, Watanabe teaches wherein the third metal line and the fourth metal line vertically extend different heights (Fig. 10, 121a, 121b, Fig. 9, 615; [0074], "FIG. 10 shows the result of depositing barrier layer metal (e.g. titanium, Ti, or titanium nitride, TiN) and bit line metal (e.g. copper, Cu) to fill trenches 615a-b…", " Bit lines 121a-b are thus formed in the trenches 615a-b...", (One metal line is below the other)).
Therefore, it would have been obvious to combine the semiconductor structure as described by the combination of Tsai, Liu, and Kim with the different heights of Watanabe so as to "maintain a minimum distance from neighboring contact plugs", (Watanabe, [0075]).
Claim(s) 15, 16, and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai (US 10074558 B1), in view of Liu (US 6150272 A), Watanabe (US 20170025354 A1), Zhang (US 20160111368 A1), and Kim (US 20100119700 A1).
Regarding dependent claim 15, Tsai, as previously modified by Liu, Watanabe, and Zhang, teaches the semiconductor structure of claim 13. Tsai further teaches further comprising: a second ILD layer disposed over the first ILD layer (Fig. 7E, 245; Col. 8, Lines 11-12, "...an operation 118 to form a second ILD layer 245…"); and Liu further teaches wherein the patterned metal structure having a top surface (Fig. 9, 12; Col. 3, Lines 59-63, "... a patterned conducting layer 12, such as a doped polysilicon, polycide layer, or metal layer is formed on the substrate surface to form portions of the devices and/or local interconnections.", (In the figure, the structure has a top surface)).
However, as previously combined, they do not teach a second metal feature disposed in the second ILD layer; and a second barrier layer on bottom and sidewall surfaces of the second metal feature, and wherein the second metal feature contacts a top surface of the patterned metal structure.
However, in the same field of endeavor, Kim teaches a second metal feature disposed in the second ILD layer (Fig. 8, 160, 140; [0043], "Next, a second metal line 160 is formed in the via hole 141…", [0036], "Then, as shown in FIG. 6, a second interlayer dielectric layer 140 is deposited…"); and a second barrier layer on bottom and sidewall surfaces of the second metal feature (Fig. 8, 150; [0041], "Thereafter, referring to FIG. 8, a second barrier layer 150 is formed in the via hole 141 and the trench 142."), and wherein the second metal feature contacts a top surface of the patterned metal structure (Fig. 2, 120, Fig. 8, 160, (Although first metal line 120 is not labeled in Fig. 8, it is evidently still there and the second metal line 160 is on top of it)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor structure as described by the combination of Tsai, Liu, Watanabe, and Zhang with the additional layers of Kim for "connecting the metal lines", (Kim, [0007]).
Regarding dependent claim 16, Tsai, as previously modified by Liu, Watanabe, Zhang, and Kim, teaches the semiconductor structure of claim 15. However, as previously combined, they do not teach further comprising a second barrier ESL layer underlying the second ILD layer, wherein the second barrier layer includes a portion interposed between and directly contacts the second barrier layer and the second ILD layer.
However, Kim further teaches further comprising a second barrier ESL layer underlying the second ILD layer (Fig. 8, 170; [0044], "...are performed to form a second etch stop layer 170 as shown in FIG. 8."), wherein the second barrier layer includes a portion interposed between and directly contacts the second barrier layer and the second ILD layer (Fig. 8, 170, 150, 140 (The ESL layer is between the barrier layer and the ILD layer)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor structure as described by the combination of Tsai, Liu, Watanabe, Zhang, and Kim with the additional layers of Kim so as to improve the distance between components (Kim, [0008]).
Regarding dependent claim 18, Tsai, as previously modified by Liu, Watanabe, and Zhang, teaches the semiconductor structure of claim 17, and further teaches further comprising a second ILD layer disposed over the first ILD layer (Fig. 7E, 245; Col. 8, Lines 11-12, "...an operation 118 to form a second ILD layer 245…").
However, as previously combined, they do not teach and a second metal layer disposed in the second ILD layer and including second metal lines, a first one of the second metal lines directly contacting a top surface of the metal plug.
However, in the same field of endeavor, Kim teaches a second metal layer disposed in the second ILD layer and including second metal lines (Fig. 8, 160, 140; [0043], "Next, a second metal line 160 is formed in the via hole 141…", [0036], "Then, as shown in FIG. 6, a second interlayer dielectric layer 140 is deposited…"), a first one of the second metal lines directly contacting a top surface of the metal plug (Fig. 2, 120, Fig. 8, 160, (Although first metal line 120 is not labeled in Fig. 8, it is evidently still there and the second metal line 160 is on top of it)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor structure as described by the combination of Tsai, Liu, Watanabe, and Zhang with the additional layers of Kim so as to improve the distance between components (Kim, [0008]).
Regarding dependent claim 19, Tsai, as previously modified by Liu, Watanabe, Zhang, and Kim, teaches the semiconductor structure of claim 18, and further teaches further comprising: a barrier layer directly disposed on bottom and sidewall surfaces of the second metal lines (Col. 7, Lines 54-56, "...a barrier layer may be formed on deposited for lining the gate trenches before filling the metal.").
Regarding dependent claim 20, Tsai, as previously modified by Liu, Watanabe, Zhang, and Kim, teaches the semiconductor structure of claim 19, and further teaches further comprising a etch stop layer (ESL) underlying the second ILD layer (Col. 6, Lines 41-43, "In an alternative embodiment, an etch stop layer may deposited on the substrate before the forming of the ILD 235…"), wherein the ESL is interposed between and directly contacts the barrier layer and the second ILD layer (Fig. 7E, Although neither layer is shown on the diagram, the specification states that the ESL is directly below the substrate 235 and that the barrier layer is directly below the metal plugs 260. This would mean that the two contact each other, and be coplanar.).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20150118842 A1.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOTHY JAMES MATTABONI whose telephone number is (571)270-0766. The examiner can normally be reached Monday-Friday 9 AM - 5 PM.
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/TIMOTHY JAMES MATTABONI/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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