Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by HIRONAKA MISAO (JP H06224463 A), cited by Applicant.
Regarding claim 1, HIRONAKA MISAO discloses a light detection device, comprising:
a semiconductor substrate (1) that has a first main surface (top) and a second main surface (Bottom) facing each other and forms an avalanche photodiode (20) and a temperature compensation diode (30) so as to be spaced apart from each other when viewed from a direction perpendicular to the first main surface [Figs. 4-5, and Machine English Translation, paragraphs 0032-0033],
wherein the semiconductor substrate includes a peripheral carrier absorbing portion (50,60) configured to absorb carriers located at a periphery, the peripheral carrier absorbing portion (50,60) being between the avalanche photodiode (20) and the temperature compensation diode (30) when viewed from the direction perpendicular to the first main surface, when viewed from the direction perpendicular to the first main surface, on a line segment connecting the avalanche photodiode and the temperature compensation diode to each other at a shortest distance, a shortest distance (S1) between the avalanche photodiode and the peripheral carrier absorbing portion is smaller than a shortest distance (S2) between the temperature compensation diode and a portion, which is closest to the avalanche photodiode, of an edge (edge closest to the photodiode 20) of the peripheral carrier absorbing portion (50,60) [See Figure 4, annotated below], and
a voltage corresponding to a breakdown voltage applied to the temperature compensation diode is applied to the avalanche photodiode as a bias voltage to provide temperature compensation for a multiplication factor of the avalanche photodiode (see description of Example 6].
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Regarding claim 12, HIRONAKA MISAO discloses a light detection device, comprising:
a semiconductor substrate (1) having a first main surface and a second main surface facing each other [Figs. 4-5], wherein the semiconductor substrate includes:
a first avalanche photodiode (20) having a light incidence surface on a side of the first main surface [Fig. 4-5];
a second avalanche photodiode (30) that is spaced apart from the first avalanche photodiode when viewed from a direction perpendicular to the first main surface and is shielded (14) from light [Fig. 4-5];
and a peripheral carrier absorbing portion (50,60) that is located between the first and second avalanche photodiodes when viewed from the direction perpendicular to the first main surface and is configured to absorb carriers located at a periphery [Figs. 4-5, respectively], and
when viewed from the direction perpendicular to the first main surface, on a line segment connecting the first avalanche photodiode (20) and the second avalanche photodiode (30) to each other at a shortest distance, a shortest distance (S1) between the first avalanche photodiode (20) and the peripheral carrier absorbing portion (50,60) is smaller than a shortest distance (S2) between the second avalanche photodiode (30) and a portion, which is closest to the first avalanche photodiode, of an edge (edge closest to the photodiode 20) of the peripheral carrier absorbing portion (50,60) [Figs. 4-5].
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-12 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-11 of U.S. Patent No. 12,322,744 in view of HIRONAKA MISAO (JP H06224463 A).
Regarding claims 1-12, U.S. Patent No. 12,322,744 discloses:
Claims
Current App.
1
2
3
4
5
6
7
8
9
10
11
12
‘803
1
3
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1
1
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2
1
However, U.S. Patent No. 12,322,744 does not disclose the “shortest” distances as recited in claims 1, 6-7, and 12.
HIRONAKA MISAO, as stated above, teaches a shortest distance (S1) between the avalanche photodiode and the peripheral carrier absorbing portion that is smaller than a shortest distance (S2) between the temperature compensation diode and a portion, which is closest to the avalanche photodiode, of an edge (edge closest to the photodiode 20) of the peripheral carrier absorbing portion (50) [See Figure 4, annotated above].
Therefore, one of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to modify U.S. Patent No. 12,322,744 by incorporating the portion and respective distances as taught by HIRONAKA MISAO because it helps to reduce cost (see Abstract).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE R DIAZ whose telephone number is (571)272-1727. The examiner can normally be reached Monday-Friday.
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/Jose R Diaz/Primary Examiner, Art Unit 2815
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