DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-9, 14-16, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Jain (U.S. PGPub 2019/0304915) in view of Chen (U.S. PGPub 2023/0317624) and Guo (U.S. PGPub 2020/0411443).
Regarding claim 1, Jain teaches a bridge chip, comprising a first side surface, a second side surface opposite to the first side surface in a first horizontal direction, a third side surface and a fourth side surface opposite to the third side surface in a second horizontal direction intersecting the first horizontal direction (Figs. 2A-2C, 110, [0041]-[0043]);
a plurality of signal wires extending across the bridge chip (118, [0041]-[0043]), and
one or more capacitor structures around the plurality of signal wires (112, [0033]-[0035]).
Jain does not explicitly teach a plurality of signal wires extending in a third horizontal direction between the first horizontal direction and the second horizontal direction, wherein first ends of the plurality of signal wires are disposed in a first line along the first side surface, and wherein second ends of the plurality of signal wires are disposed in a second line along the second side surface.
Jain teaches wherein the region comprising signal wires may extend to an edge of the bridge die (Fig. 2C, [0043]).
Chen teaches diagonal wiring traces (Fig. 2B, [0023]), extending in a direction between the chip x/y directions).
Guo teaches wherein signal wires on a bridge chip would be understood by a person of ordinary skill to have “virtually any footprint and trace pathways, such as straight, bent, curved, zigzag, etc” ([0048], 35, [0047]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Chen and Guo with Jain such that the device comprises a plurality of signal wires extending in a third horizontal direction between the first horizontal direction and the second horizontal direction, wherein first ends of the plurality of signal wires are disposed in a first line along the first side surface, and wherein second ends of the plurality of signal wires are disposed in a second line along the second side surface for the purpose of providing increased mechanical integrity (Chen, [0023]) and because modifying the placement and shape of the wiring was known to be obvious (Guo, [0048]).
Regarding claim 2, it would have been obvious to a person having ordinary skill in the art to further combine the teachings of Jain, Chen, and Guo such that the first horizontal direction and the second horizontal direction are orthogonal to each other, and wherein the third horizontal direction is inclined at 45 degrees to the first horizontal direction for the reasons set forth in the rejection of claim 1.
Regarding claim 3, the combination of Jain, Chen, and Guo teaches wherein the bridge chip comprises a first area and a second area defined by dividing a plane of the bridge chip, wherein the plurality of signal wires are disposed in the first area, and wherein the plurality of signal wires are not disposed in the second area (Jain, 116, [0041]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Jain, Chen, and Guo for the reasons set forth in the rejection of claim 1.
Regarding claim 4, the combination of Jain, Chen, and Guo teaches wherein the one or more capacitor structures are disposed in the second area (Jain, [0041]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Jain, Chen, and Guo for the reasons set forth in the rejection of claim 1.
Regarding claim 5, the combination of Jain, Chen, and Guo teaches wherein the bridge chip comprises a silicon bridge chip (Jain, Fig. 2A, 110, [0032]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Jain, Chen, and Guo for the reasons set forth in the rejection of claim 1.
Regarding claim 6, the combination of Jain, Chen, and Guo teaches wherein the one or more capacitor structures comprise at least one of metal-insulator-metal (MIM) capacitors, deep trench capacitors (DTC), or integrated stack capacitors (ISC) (Jain, [0033]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Jain, Chen, and Guo for the reasons set forth in the rejection of claim 1.
Regarding claim 7, Jain teaches a semiconductor package (Figs. 2A-2C, 100), comprising:
a substrate comprising a cavity (102, [0032]),
a bridge die disposed within the cavity, wherein the bridge die comprises a plurality of signal wires and one or more capacitor structures (Figs. 2A-2C, 110, 118, [0041]-[0043]; 112, [0033]-[0035]);
a first semiconductor die on the substrate and the bridge die and a second semiconductor die on the substrate and the bridge die, wherein the second semiconductor die is spaced apart from the first semiconductor die in a first horizontal direction, wherein the plurality of signal wires electrically couple the first semiconductor die with the second semiconductor die (Figs. 2A-2C, [0041]-[0043]), and
wherein the one or more capacitor structures are disposed around the plurality of signal wires (Figs. 2A-2C, 112/116).
Jain does not explicitly wherein the plurality of signal wires extend in a third horizontal direction between the first horizontal direction and a second horizontal direction orthogonal to the first horizontal direction.
Jain teaches wherein the region comprising signal wires may extend to an edge of the bridge die (Fig. 2C, [0043]).
Chen teaches diagonal wiring traces (Fig. 2B, [0023]), extending in a direction between the chip x/y directions).
Guo teaches wherein signal wires on a bridge chip would be understood by a person of ordinary skill to have “virtually any footprint and trace pathways, such as straight, bent, curved, zigzag, etc” ([0048], 35, [0047]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Chen and Guo with Jain such that the plurality of signal wires extend in a third horizontal direction between the first horizontal direction and a second horizontal direction orthogonal to the first horizontal direction for the purpose of providing increased mechanical integrity (Chen, [0023]) and because modifying the placement and shape of the wiring was known to be obvious (Guo, [0048]).
Regarding claim 8, the combination of Jain, Chen, and Guo teaches wherein at least one corner of a footprint of the first semiconductor die at least partially overlaps a footprint of the bridge die and wherein at least one corner of the footprint of the bridge die at least partially overlaps the footprint of the first semiconductor die (Jain, Fig. 2A). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Jain, Chen, and Guo for the reasons set forth in the rejection of claim 7.
Regarding claim 9, the combination of Jain, Chen, and Guo teaches wherein at least one corner of a footprint of the second semiconductor die at least partially overlaps a footprint of the bridge die, and wherein at least one corner of the footprint of the bridge die at least partially overlaps the footprint of the second semiconductor die (Jain, Fig. 2A). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Jain, Chen, and Guo for the reasons set forth in the rejection of claim 7.
Regarding claim 14, the combination of Jain, Chen, and Guo teaches wherein the first semiconductor die comprises a logic die (Jain, [0034]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Jain, Chen, and Guo for the reasons set forth in the rejection of claim 7.
Regarding claim 15, the combination of Jain, Chen, and Guo teaches wherein the second semiconductor die comprises a high bandwidth memory (HBM) (Jain, [0034]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Jain, Chen, and Guo for the reasons set forth in the rejection of claim 7.
Regarding claim 16, the combination of Jain, Chen, and Guo teaches wherein the substrate comprises at least one of a printed circuit board, a redistribution structure, or an interposer (Jain, [0038]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Jain, Chen, and Guo for the reasons set forth in the rejection of claim 7.
Regarding claim 19, Jain teaches a semiconductor package (Figs. 2A-2C, 100), comprising:
a substrate comprising a cavity (102, [0032]),
a bridge die disposed within the cavity, wherein the bridge die comprises a plurality of signal wires and one or more capacitor structures (Figs. 2A-2C, 110, 118, [0041]-[0043]; 112, [0033]-[0035]);
a first semiconductor die on the substrate and the bridge die and a second semiconductor die on the substrate and the bridge die and spaced apart from the first semiconductor die in a first horizontal direction, (Figs. 2A-2C, [0041]-[0043]),
a plurality of first connection members between the bridge die and the first semiconductor die and a plurality of second connection members between the bridge die and the second semiconductor die (108, [0038], see Fig. 1),
wherein each of the plurality of signal wires electrically couples a corresponding first connection member of the plurality of first connection members with a corresponding second connection member of the plurality of second connection members (118, [0041]-[0043]),
wherein the one or more capacitor structures are disposed around the plurality of signal wires (Figs. 2A-2C, 112/116).
Jain does not explicitly wherein the plurality of signal wires extend in a third horizontal direction between the first horizontal direction and a second horizontal direction orthogonal to the first horizontal direction, wherein the plurality of first connection members are disposed in a first line along a side surface of the first semiconductor die facing the second semiconductor die, and wherein the plurality of second connection members are disposed in a second line along a side surface of the second semiconductor die facing the first semiconductor die.
Jain teaches wherein the region comprising signal wires may extend to an edge of the bridge die (Fig. 2C, [0043]).
Chen teaches diagonal wiring traces extending in a direction between the chip x/y directions) connecting first and second connection members disposed in respective first and second lines along the side surfaces of each die (Fig. 2B, [0023]).
Guo teaches wherein signal wires on a bridge chip would be understood by a person of ordinary skill to have “virtually any footprint and trace pathways, such as straight, bent, curved, zigzag, etc” ([0048], 35, [0047]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Chen and Guo with Jain such that the plurality of signal wires extend in a third horizontal direction between the first horizontal direction and a second horizontal direction orthogonal to the first horizontal direction, wherein the plurality of first connection members are disposed in a first line along a side surface of the first semiconductor die facing the second semiconductor die, and wherein the plurality of second connection members are disposed in a second line along a side surface of the second semiconductor die facing the first semiconductor die for the purpose of providing increased mechanical integrity (Chen, [0023]) and because modifying the placement and shape of the wiring was known to be obvious (Guo, [0048]).
Regarding claim 20, it would have been obvious to a person having ordinary skill in the art to further combine the teachings of Jain, Chen, and Guo such that each of the plurality of signal wires comprises a first portion coupled with the corresponding first connection member and extending in the first horizontal direction, a second portion extending in the third horizontal direction, and a third portion coupled with the corresponding second connection member and extending in the first horizontal direction for the reasons set forth in the rejection of claim 19.
Claims 10-13 are rejected under 35 U.S.C. 103 as being unpatentable over Jain (U.S. PGPub 2019/0304915) in view of Chen (U.S. PGPub 2023/0317624) and Guo (U.S. PGPub 2020/0411443) and further in view of Lee (U.S. PGPub 2021/0043557).
Regarding claim 10, the combination of Jain, Chen, and Guo does not explicitly teach wherein the bridge die further comprises one or more through silicon vias disposed around the plurality of signal wires.
Lee teaches a bridge die (Fig. 16A, [0289]; Fig. 30, [0435], 471) comprising a capacitor ([0289], 401, Fig. 3E) and one or more through silicon vias disposed adjacent to the capacitor ([0289], 157, Figs. 3E-3F).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Lee with Jain, Chen, and Guo such that the bridge die further comprises one or more through silicon vias disposed around the plurality of signal wires for the purpose of providing a bridge die with horizontal and vertical signal transmission (Lee, [0287]).
Regarding claim 11, the combination of Jain, Chen, Guo, and Lee teaches wherein the one or more through silicon vias electrically couple at least one of the first semiconductor die and the second semiconductor die with the substrate (Lee, Fig. 30, [0440]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Jain, Chen, Guo, and Lee for the reasons set forth in the rejection of claim 10.
Regarding claim 12, the combination of Jain, Chen, Guo, and Lee teaches wherein each of the one or more through silicon vias is electrically coupled with a corresponding capacitor structure of the one or more capacitor structures (Lee, Fig. 3E, [0176]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Jain, Chen, Guo, and Lee for the reasons set forth in the rejection of claim 10.
Regarding claim 13, the combination of Jain, Chen, Guo, and Lee teaches wherein the one or more through silicon vias are configured to transmit power (Lee, [0113], [0443]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Jain, Chen, Guo, and Lee for the reasons set forth in the rejection of claim 10.
Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Jain (U.S. PGPub 2019/0304915) in view of Chen (U.S. PGPub 2023/0317624) and Guo (U.S. PGPub 2020/0411443) and further in view of Rubin (U.S. PGPub 2021/0265275).
Regarding claim 17, the combination of Jain, Chen, and Guo does not explicitly teach an adhesive member between the bridge die and a bottom surface of the cavity.
Rubin teaches a bridge chip embedded in a cavity of a substrate, wherein an adhesive member is between the bridge die and a bottom surface of the cavity (Fig. 1E, 110, 100, 112, [0043]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Rubin with Jain, Chen, and Guo such that the device comprises an adhesive member between the bridge die and a bottom surface of the cavity for the purpose of attaching the bridge to the substrate cavity (Rubin, [0043]).
Regarding claim 18, the combination of Jain, Chen, and Guo does not explicitly teach a plurality of connection members between the bridge die and a bottom surface of the cavity.
Rubin teaches a bridge chip embedded in a cavity of a substrate, wherein a plurality of connection members between the bridge die and a bottom surface of the cavity (Fig. 4B, 110, 410, [0072]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Rubin with Jain, Chen, and Guo such that the device comprises a plurality of connection members between the bridge die and a bottom surface of the cavity for the purpose of providing vertical connections through the bridge (Rubin, [0072]).
Conclusion
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/ALIA SABUR/Primary Examiner, Art Unit 2812
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