Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 6-12, and 14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hung et al., US 2017/0229426.
Hung et al. shows the invention as claimed including a semiconductor device assembly, comprising:
A first redistribution layer 160/150 and a second redistribution layer 150/160;
A first semiconductor die (for example, 120) disposed between the first redistribution layer and the second redistribution layer, and connected to the first redistribution layer, the first semiconductor die 120/110 having an active surface and a back surface opposite the active surface of the first semiconductor die; and a second semiconductor die 110/120 disposed between the first redistribution layer and the second redistribution layer, and connected to the second redistribution layer, the second semiconductor die having an active surface and a back surface opposite the active surface of the semiconductor die, and the second semiconductor die stacked on the first semiconductor die with the back surface of the second semiconductor die facing the back surface of the first semiconductor die (see, for example, figs. 1, 4a-4h and paragraphs 0013-0032).
Concerning dependent claims 2 and 11, note that Hung et al. discloses wherein the active surface of the first semiconductor die faces the first redistribution layer, and the active surface of the second semiconductor die faces the second redistribution layer (see paragraphs 0024-0025, for example, and fig. 2).
As to dependent claim 3, Hung et al. discloses wherein the first semiconductor die and the second semiconductor die are vertically symmetrical (see fig. 2).
Concerning dependent claim 4, note that Hung et al. discloses wherein the semiconductor device assembly further comprises a second back-to-back die stack disposed between the first redistribution layer and the second redistribution layer (see, for example, figs. 4a-4h and their descriptions).
With respect to dependent claim 6, note that Hung et al. discloses wherein the active surface of the second semiconductor die has one or more interconnects (for example, 124) that directly connect to electrical connections of the second redistribution layer free of solder joints (see, for example, paragraph 0034).
Regarding dependent claim 7, Hung et al. discloses a mold compound 130 between the first redistribution layer and the second redistribution layer and surrounding the first semiconductor die and the second semiconductor die (see fig. 2).
As to dependent claim 9, note that Hung et al. discloses a die attach film 170 between the first semiconductor die and the second semiconductor die (see paragraph 0027 and fig. 2).
Regarding independent claim 10, Hung et al. shows the invention as claimed including a memory device, comprising:
A first redistribution layer 150/160 and a second redistribution layer 160/150 separated by a molding layer 130;
A first memory die 120/110 disposed in the molding layer between the first and second redistribution layers;
A second memory die 110/120 disposed in the molding layer between the first and second redistribution layers, wherein the first and second memory dies are stacked back to back (see, for example, figs. 1, 4a-4h and paragraphs 0013-0032).
With respect to dependent claim 11, note that Hung et al. discloses wherein an active surface of the first memory die faces the first redistribution layer, and an active surface of the second memory die faces the second redistribution layer (see fig. 2).
Concerning dependent claim 12, note that in Hung et al. the first memory die is connected to the first redistribution layer, and the second memory die is connected to the second redistribution layer (see fig. 2).
As to dependent claim 14, note that Hung et al. discloses one or more through mold interconnects 140 electrically connecting the first redistribution layer 150/160 to the second redistribution layer 160/150 (see figs. 2 and paragraphs 0018).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 5, 13, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hung et al., US 2017/0229426 in view of Yang et al., US 2009/0127696.
Hung et al. is applied as above but does not expressly disclose wherein the active surface of the first semiconductor die has one or more interconnects that connect to electrical connections of the first redistribution layer via solder joints, a plurality of solder balls electrically connected to the second redistribution layer, and wherein the first memory die has one or more first interconnects that connect to electrical connections of the first redistribution layer via solder joints. Yang et al. discloses where the active surface of a semiconductor die (for example, 2c) is connected to a redistribution layer using solder joints 40 (see, for example, figs. 3-5 and their descriptions). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the primary reference of Hung et al. so as to form the claimed solder connections because Yang et al. shows this to be a suitable method with which to ensure electrical connections.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent 6,800,930 discloses a packaged device with a back redistribution layer with solder connections (see fig. 3).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD A BOOTH whose telephone number is (571)272-1668. The examiner can normally be reached Monday to Friday, 8:30 to 5:00.
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/RICHARD A BOOTH/ Primary Examiner, Art Unit 2812
September 28, 2026
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